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SRAM cell with dynamic split ground and split wordline

  • US 10,347,327 B2
  • Filed: 10/30/2017
  • Issued: 07/09/2019
  • Est. Priority Date: 12/02/2014
  • Status: Active Grant
First Claim
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1. A memory cell, comprising:

  • cross coupled inverters comprising PFETs and NFETs;

    a bitline left (BL) which accesses a first inverter of the cross coupled inverters by enabling a first access transistor;

    a bitline right (BR) which accesses a second inverter of the cross coupled inverters by enabling a second access transistor;

    a left side cell node (CL) across the first access transistor from the BL;

    a right side cell node (CR) across the second access transistor from the BR; and

    a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters,wherein;

    the GNDL and the GNDR are separate vertical SRAM GND buses;

    the GNDR and GNDL allow for differential signaling, andduring global reset of memory array to zero state, the GNDL is raised to Vdd to pull down the CR and push up the CL.

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