SRAM cell with dynamic split ground and split wordline
First Claim
1. A memory cell, comprising:
- cross coupled inverters comprising PFETs and NFETs;
a bitline left (BL) which accesses a first inverter of the cross coupled inverters by enabling a first access transistor;
a bitline right (BR) which accesses a second inverter of the cross coupled inverters by enabling a second access transistor;
a left side cell node (CL) across the first access transistor from the BL;
a right side cell node (CR) across the second access transistor from the BR; and
a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters,wherein;
the GNDL and the GNDR are separate vertical SRAM GND buses;
the GNDR and GNDL allow for differential signaling, andduring global reset of memory array to zero state, the GNDL is raised to Vdd to pull down the CR and push up the CL.
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Accused Products
Abstract
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.
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Citations
10 Claims
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1. A memory cell, comprising:
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cross coupled inverters comprising PFETs and NFETs; a bitline left (BL) which accesses a first inverter of the cross coupled inverters by enabling a first access transistor; a bitline right (BR) which accesses a second inverter of the cross coupled inverters by enabling a second access transistor; a left side cell node (CL) across the first access transistor from the BL; a right side cell node (CR) across the second access transistor from the BR; and a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters, wherein; the GNDL and the GNDR are separate vertical SRAM GND buses; the GNDR and GNDL allow for differential signaling, and during global reset of memory array to zero state, the GNDL is raised to Vdd to pull down the CR and push up the CL. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification