Low temperature poly silicon backboard, method for manufacturing the same and light-emitting device

• US 10,347,532 B2
• Filed: 10/15/2015
• Issued: 07/09/2019
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Xu, Xiaowei, Liu, Libin, Li, Liangjian, Long, Chunping
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US15/104,551
• Publication Number:
  US 20180204769A1
• Time in Patent Office: 1,363 Days
• Field of Search: 257 72, 257 79, 349116
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

The present disclosure provides a Low Temperature Poly Silicon (LTPS) backboard, a method for manufacturing the LTPS, and a light-emitting device. The LTPS backboard includes: a base substrate, and a thin film transistor (TFT) and a light blocking layer that are arranged above the base substrate, wherein the light blocking layer is arranged above the TFT, and the light blocking layer is configured for preventing an irradiation light from irradiating onto the TFT.

Claims

1. A Low Temperature Poly Silicon (LTPS) backboard, comprising:

a base substrate; and

a thin film transistor (TFT) and a light blocking layer that are arranged above the base substrate,

wherein the light blocking layer is arranged above the TFT,

the light blocking layer continuously covers outer surfaces of a source/drain electrode of the TFT and an intermediate insulation layer adjacent to the source/drain electrode, and the light blocking layer is in direct contact with the outer surfaces of the source/-drain electrode and the intermediate insulation layer,

the light blocking layer comprises a light absorption layer, and the light absorption layer is configured to absorb ultraviolet light, and

the light blocking layer further comprises a light shielding layer, the light shielding layer has a structure of a composite layer consisting of an insulation layer and a metallic layer, and the insulation layer is arranged between the metallic layer and the source/drain electrode.

2. The LTPS backboard according to claim 1, wherein the light absorption layer has a thickness of 200 nm to 440 nm.

3. The LTPS backboard according to claim 1, wherein a material of the light absorption layer comprises an organic material or a mixture of a plurality of organic materials.

4. The LTPS backboard according to claim 3, wherein the organic material comprises P3HT or F8T2.

5. The LTPS backboard according to claim 1, wherein a material of the light absorption layer comprises an inorganic material or a mixture of a plurality of inorganic materials.

6. The LTPS backboard according to claim 5, wherein the inorganic material comprises zinc oxide or titanium oxide.

7. The LTPS backboard according to claim 1, wherein the light shielding layer has a thickness of 50 nm to 500 nm.

8. The LTPS backboard according to claim 1, wherein the TFT comprises:

an active layer arranged above the base substrate, wherein a gate insulation layer is arranged on the active layer;

a gate electrode arranged above the gate insulation layer, wherein an intermediate insulation layer is arranged on the gate electrode; and

the source/drain electrode arranged on the intermediate insulation layer and connected to the active layer through a first via hole arranged in the intermediate insulation layer and the gate insulation layer, wherein the light blocking layer is arranged on the source/drain electrode.

9. The LTPS backboard according to claim 1, wherein a planarization layer is arranged on the light blocking layer.

10. The LTPS backboard according to claim 9, wherein the planarization layer is made of a photosensitive material.

11. The LTPS backboard according to claim 9, wherein a first electrode is arranged on the planarization layer, the first electrode is connected to a source/drain electrode through a second via hole arranged in the planarization layer and the light blocking layer, and a pixel definition layer is arranged on the first electrode.

12. The LTPS backboard according to claim 8, further comprising a buffer layer arranged on the base substrate, wherein the active layer is arranged on the buffer layer.

17. The LTPS backboard according to claim 1, wherein the light absorption layer is configured to absorb ultraviolet light having a wavelength of 200 nm to 400 nm, and

wherein the light blocking layer covers an upper surface, a left side surface, and a right side surface of the source/drain electrode.

18. The LTPS backboard according to claim 1, wherein the light blocking layer is of a continuous structure.

13. A light-emitting device, comprising:

a Low Temperature Poly Silicon (LTPS) backboard; and

a pixel structure,

wherein the LTPS backboard comprises;

a base substrate; and

a thin film transistor (TFT) and a light blocking layer that are arranged above the base substrate,

wherein the light blocking layer is arranged above the TFT,

the light blocking layer continuously covers outer surfaces of a source/drain electrode of the TFT and an intermediate insulation layer adjacent to the source/drain electrode, and the light blocking layer is in direct contact with the outer surfaces of the source/drain electrode and the intermediate insulation layer,

the light blocking layer comprises a light absorption layer, and the light absorption layer is configured to absorb ultraviolet light,

the pixel structure is made of an organic light emitting material, and

the light blocking layer further comprises a light shielding layer, the light shielding layer has a structure of a composite layer consisting of an insulation layer and a metallic layer, and the insulation layer is arranged between the metallic layer and the source/drain electrode.

14. The light-emitting device according to claim 13, further comprising a second electrode arranged above the pixel structure.

15. A method for manufacturing a Low Temperature Poly Silicon (LTPS) backboard, comprising:

forming a thin film transistor (TFT) above a base substrate; and

forming a light blocking layer above the TFT,

wherein the light blocking layer continuously covers outer surfaces of a source/drain electrode of the TFT and an intermediate insulation layer adjacent to the source/drain electrode, and the light blocking layer is in direct contact with the outer surfaces of the source/drain electrode and the intermediate insulation layer,

wherein the light blocking layer comprises a light absorption layer, and the light absorption layer is configured to absorb ultraviolet light, and

wherein the light blocking layer further comprises a light shielding layer, the light shielding layer has a structure of a composite layer consisting of an insulation layer and a metallic layer, and the insulation layer is arranged between the metallic layer and the source/drain electrode.

16. The method according to claim 15, further comprising:

forming a planarization layer on the light blocking layer;

forming a second via hole in the planarization layer and the light blocking layer,

forming a first electrode on the planarization layer, wherein the first electrode is connected to a source/drain electrode of the TFT through the second via hole; and

forming a pixel definition layer on the first electrode.