Semiconductor packages having redistribution substrate

• US 10,347,611 B2
• Filed: 01/16/2017
• Issued: 07/09/2019
• Est. Priority Date: 01/14/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jichul, Kim, Jae Choon, Ryu, Hansung, Cho, KyongSoon, Cho, YoungSang, Yoon, Yeo-Hoon
• Primary Examiner(s): Ho, Anthony
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US15/406,925
• Publication Number:
  US 20170207205A1
• Time in Patent Office: 904 Days
• Field of Search: 257774
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/95001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

Claims

1. A semiconductor package comprising:

a redistribution substrate;

an interconnect substrate on the redistribution substrate, the interconnect substrate including a hole penetrating thereinside;

a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate;

a metal layer on the semiconductor chip; and

a mold layer in a gap between the semiconductor chip and the interconnect substrate,

wherein the interconnect substrate includes base layer and a conductive member extending through the base layer,

wherein a top surface of the interconnect substrate is positioned at a level lower than that of a top surface of the metal layer,

wherein the mold layer covers the top surface of the interconnect substrate and the top surface of the metal layer,

wherein the metal layer has a width and a planar shape substantially the same as those of the semiconductor chip,

wherein the conductive member comprises;

a lower pad on a bottom surface of the interconnect substrate;

vias and a line pattern in the base layer; and

an upper pad on the top surface of the interconnect substrate;

wherein the upper pad is connected to the lower pad through the vias and the line pattern, and

wherein the upper pad is not aligned with the lower pad in a vertical direction.

2. The semiconductor package of claim 1, further comprising an adhesive layer connecting and in contact with the semiconductor chip and the metal layer,

wherein the adhesive layer includes a thermosetting polymer or a thermoplastic polymer.

3. The semiconductor package of claim 1, wherein the redistribution substrate comprises insulative patterns and a conductive pattern between the insulative patterns,

wherein the metal layer and the conductive pattern have a coefficient of thermal expansion greater than that of the semiconductor chip, and

wherein the metal layer has a thermal conductivity greater than that of the semiconductor chip.

4. The semiconductor package of claim 1, further comprising an upper package on the interconnect substrate and the metal layer,

wherein the upper package is electrically connected to the conductive member.

18. The semiconductor package of claim 1, wherein the metal layer is in contact with an upper surface of the semiconductor chip.

19. The semiconductor package of claim 1, further comprising a seed layer formed on and in contact with an upper surface of the semiconductor chip.

5. A semiconductor package comprising:

a substrate;

a semiconductor chip on the substrate;

a first metal layer on the semiconductor chip;

an interconnect substrate that is disposed side by side with the semiconductor chip on the substrate and surrounds the semiconductor chip in plan view;

a mold layer in a gap between the semiconductor chip and the interconnect substrate; and

a carbon layer including at least one of carbon nanotube, graphene, and graphite disposed on and contacting a top surface of the first metal layer,

wherein the interconnect substrate includes a base layer and a conductive member extending through the base layer,

wherein the carbon layer has a width and a planar shape substantially the same as a width and a planar shape of the first metal layer, respectively,

wherein the mold layer covers the top surface of the first metal layer and a top surface of the interconnect substrate, and

wherein the width and the planar shape of the first metal layer are substantially the same as those of the semiconductor chip.

6. The semiconductor package of claim 5,

wherein the interconnect substrate comprises a hole penetrating thereinside, and

wherein the semiconductor chip is provided in the hole of the interconnect substrate.

7. The semiconductor package of claim 6, wherein a plurality of semiconductor chips are provided in the hole.

8. The semiconductor package of claim 5, wherein the conductive member comprises a ground pattern and a signal pattern,

wherein the first metal layer extends onto and is connected to the ground pattern, and

wherein the first metal layer is insulated from the signal pattern.

9. The semiconductor package of claim 8, further comprising a second metal layer disposed on the semiconductor chip and spaced apart from the first metal layer,

wherein the second metal layer extends onto and is connected to the signal pattern, and

wherein the second metal layer is insulated from the ground pattern.

10. The semiconductor package of claim 5, further comprising an interposer layer on the interconnect substrate and the semiconductor chip,

wherein the first metal layer is provided in the interposer layer.

11. The semiconductor package of claim 10, wherein the interposer layer comprises:

an insulation layer including a first surface and a second surface facing each other, wherein the first metal layer is provided on the first surface of the insulation layer;

a metal pattern on the first surface of the insulation layer; and

metal vias that are provided in the insulation layer and respectively disposed on the first metal layer and the metal pattern.

12. The semiconductor package of claim 10, wherein the interposer layer comprises:

an insulation layer including a first surface and a second surface facing each other, wherein the first metal layer is provided on the first surface of the insulation layer;

a metal pattern on the second surface of the insulation layer; and

metal vias that penetrate the insulation layer and are respectively connected to the first metal layer and the metal pattern.

13. The semiconductor package of claim 5, wherein the interconnect substrate has a rectangular shape in plan view and is provided in plural on the substrate.

14. A semiconductor package comprising:

a redistribution substrate;

an interconnect substrate on the redistribution substrate, the interconnect substrate including a hole penetrating thereinside;

a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate;

a metal layer on the semiconductor chip; and

a mold layer in a gap between the semiconductor chip and the interconnect substrate,

wherein the interconnect substrate includes base layers and a conductive member extending through the base layers,

wherein a top surface of the interconnect substrate is positioned at a level even with or above that of a top surface of the metal layer,

wherein the mold layer covers the top surface of the metal layer and the top surface of the interconnect substrate, and

wherein the metal layer has a width and a planar shape substantially the same as those of the semiconductor chip.

15. The semiconductor package of claim 14, further comprising an adhesive layer connecting and in contact with the semiconductor chip and the metal layer, wherein the adhesive layer includes a thermosetting polymer or a thermoplastic polymer.

16. The semiconductor package of claim 14, wherein the conductive member comprises:

a lower pad on a bottom surface of the interconnect substrate;

a line pattern between the base layers;

vias penetrating the base layers; and

an upper pad on the top surface of the interconnect substrate,

wherein the upper pad is connected to the lower pad through the vias and the line pattern,

wherein the upper pad is not aligned with the lower pad.

17. The semiconductor package of claim 14, wherein the redistribution substrate comprises insulative patterns and a conductive pattern between the insulative patterns,

wherein the metal layer and the conductive pattern have a coefficient of thermal expansion greater than that of the semiconductor chip, and

wherein the metal layer has a thermal conductivity greater than that of the semiconductor chip.