Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 10,347,636 B2
• Filed: 01/04/2019
• Issued: 07/09/2019
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/239,758
• Publication Number:
  US 20190139962A1
• Time in Patent Office: 186 Days
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. A semiconductor memory device comprising:

a plurality of semiconductor memory cells connected in series, wherein at least two of said memory cells each include;

a floating body region configured to store data as charge therein to define a state of said memory cell selected from at least first and second states, wherein current flow through said memory cell is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of said memory cell.

2. The semiconductor memory device of claim 1, wherein said at least two memory cells each further comprise first and second conductive regions interfacing with said floating body region.

3. The semiconductor memory device of claim 2, wherein said at least two memory cells each further comprise a gate region positioned between said first and second conductive regions.

4. The semiconductor memory device of claim 2, wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types, said first conductive region, said second conductive region, and said back-bias region have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

5. The semiconductor memory device of claim 4, wherein said at least two memory cells each further comprise a substrate having said first conductivity type.

6. The semiconductor memory device of claim 1, wherein when a first memory cell of said at least two of said memory cells is in one of said first and second states and a second memory cell of said at least two of said memory cells is in one of said first and second states, applications of voltage to said back-bias region maintain said first and second memory cells in said states.

7. The semiconductor memory device of claim 6, wherein said state of said first memory cell is different from said state of said second memory cell.

8. A semiconductor memory device comprising:

a plurality of semiconductor memory cells connected in series, wherein at least two of said memory cells each include;

a floating body region configured to store data as charge therein;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region;

wherein said back-bias region is configured to establish at least two different stable floating body charge levels by application of voltage to said back-bias region;

wherein current flow through said memory cell is larger when said memory cell is in one of said at least two different stable floating body charge levels than when said memory cell is in the other of said at least two different stable floating body charge levels.

9. The semiconductor memory device of claim 8, wherein said voltage applied to said back-bias region is a constant positive voltage bias.

10. The semiconductor memory device of claim 8, wherein said voltage applied to said back-bias region is a periodic pulse of positive voltage.

11. The semiconductor memory device of claim 8, wherein when a first memory cell of said at least two of said memory cells is in one of said at least two different stable floating body charge levels and a second memory cell of said at least two of said memory cells is in one of said at least two different stable floating body charge levels, applications of voltage to said back-bias region maintain said first and second memory cells at said stable floating body charge levels.

12. The semiconductor memory device of claim 11, wherein said first memory cell is at a first stable floating body charge level and said second memory cell is at a second stable floating body charge level and said first stable floating body charge level is different from said second stable floating body charge level.

13. A semiconductor memory device comprising:

a plurality of semiconductor memory cells connected in series, wherein at least two of said memory cells each include;

a floating body region configured to store data as charge therein to define a state of said memory cell selected from at least first and second states;

wherein current flow through said memory cell is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region commonly connected to said at least two of said memory cells.

14. The semiconductor memory device of claim 13, wherein each said floating body region has a first conductivity type selected from p-type and n-type conductivity types, each said first region, second region, and back-bias region have a second conductivity type selected from p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

15. The semiconductor memory device of claim 13, wherein said at least two memory cells each further comprise a substrate having a first conductivity type selected from p-type and n-type conductivity types.

16. The semiconductor memory device of claim 13, wherein application of voltage to said back-bias region maintains current states of each said memory cell connected thereto.

17. The semiconductor memory device of claim 16, wherein said application of voltage is applied as a constant positive voltage bias.

18. The semiconductor memory device of claim 16, wherein said application of voltage is applied as a periodic pulse of positive voltage bias.

19. The semiconductor memory device of claim 13, wherein when a first memory cell of said at least two of said memory cells is in one of said first and second states and a second memory cell of said at least two of said memory cells is in one of said first and second states, application of voltage to said back-bias region maintains said first memory cell and said second memory cell in said states.

20. The semiconductor memory device of claim 19, wherein said first memory cell is in said first state, said second memory cell is in said second state, and said first state is different from said second state.