Integrated assemblies, and methods of forming integrated assemblies

• US 10,347,639 B1
• Filed: 04/19/2018
• Issued: 07/09/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ujihara, Shingo, Taketani, Hiroaki
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US15/957,589
• Time in Patent Office: 446 Days
• Field of Search: 257192
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 : Bit line contacts
• CPC Class Codes: H10B 12/488 : Word lines
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures

Abstract

Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.

Claims

1. An integrated assembly, comprising:

a first semiconductor material configured to comprise a pair of pedestals;

the pedestals having upper regions which are separated from one another by a space, and having lower regions which join to one another at a floor region beneath the space;

the pedestals being a first pedestal and a second pedestal;

a second semiconductor material configured as a bridge extending between the pedestals;

the bridge being above the floor region, and being spaced from the floor region by an intervening gap;

the bridge having a first end adjacent the first pedestal, a second end adjacent the second pedestal, and body region between the first and second ends;

the body region having an outer periphery which surrounds the body region;

a first source/drain region within the first pedestal, a second source/drain region within the second pedestal, and a channel region within the bridge;

a dielectric material outward of the bridge and extending entirely around the outer periphery of the body region of the bridge; and

a conductive material outward of the dielectric material and extending entirely around the outer periphery of the body region of the bridge;

the conductive material comprising a transistor gate which gatedly couples the first and second source/drain regions to one another through the channel region.

2. The integrated assembly of claim 1 wherein the second semiconductor material comprises a different composition relative to the first semiconductor material.

3. The integrated assembly of claim 1 wherein the second semiconductor material comprises a same composition as the first semiconductor material.

4. The integrated assembly of claim 1 wherein the first and second semiconductor materials both comprise silicon.

5. The integrated assembly of claim 1 comprising a charge-storage device coupled with the first source/drain region, and comprising a bitline coupled with the second source/drain region.

6. The integrated assembly of claim 1 wherein the conductive material is a metal-containing material.

7. A memory array, comprising:

active regions;

each of the active regions including a first semiconductor material configured to comprise three pedestals;

the pedestals being a first pedestal, a second pedestal and a third pedestal;

the first and second pedestals having upper regions separated from one another by a first space, and having lower regions joining to one another at a first floor region beneath the first space;

the second and third pedestals having upper regions separated from one another by a second space, and having lower regions joining to one another at a second floor region beneath the second space;

first bridges extending between the first and second pedestals;

the first bridges being above the first floor regions, and being spaced from the first floor regions by first intervening gaps;

the first bridges each having a first body region, and each having a first outer periphery which surrounds the first body region;

second bridges extending between the second and third pedestals;

the second bridges being above the second floor regions, and being spaced from the second floor regions by second intervening gaps;

the second bridges each having a second body region, and each having a second outer periphery which surrounds the second body region;

first, second and third source/drain regions within the first, second and third pedestals, respectively, of each of the active regions;

the first and second bridges comprising second semiconductor material;

first channel regions within each of the first bridges;

second channel regions within each of the second bridges;

wordlines having gate regions which extend entirely around the first and second outer peripheries;

charge-storage devices coupled with the first and third source/drain regions; and

bitlines coupled with the second source/drain regions.

8. The memory array of claim 7 comprising dielectric material extending entirely around the first and second outer peripheries;

the dielectric material being between the wordlines and the second semiconductor material.

9. The memory array of claim 8 wherein the dielectric material comprises silicon dioxide.

10. The memory array of claim 7 wherein the wordlines comprise metal.

11. The memory array of claim 7 wherein the second semiconductor material comprises a different composition relative to the first semiconductor material.

12. The memory array of claim 7 wherein the second semiconductor material comprises a same composition as the first semiconductor material.

13. The memory array of claim 7 wherein the first and second semiconductor materials both comprise silicon.

14. A method of forming an integrated assembly, comprising:

providing a substrate comprising, along a cross-section, active regions spaced from one another by intervening locations;

the cross-section being along a plane which extends along a first direction;

forming trenches extending along a second direction which crosses the first direction and intersects the first plane;

the trenches comprising a pair of trenches extending through one of the active regions along the cross-section, and a pair of trenches passing along outer edges of said one of the active regions along the cross-section;

the trenches passing through said one of the active regions being first and second trenches;

the trenches passing along the outer edges of said one of the active regions being third and fourth trenches;

forming spacers along bottom regions of the first and second trenches;

forming semiconductor material over the spacers and configured as bridges;

the bridges being a first bridge within the first trench and a second bridge within the second trench;

the first bridge having a first body region and having a first outer periphery which surrounds the first body region;

the second bridge having a second body region and having a second outer periphery which surrounds the second body region;

removing the spacers from under the bridges;

forming dielectric material to surround the first and second outer peripheries of the first and second bridges; and

after forming the dielectric material, forming wordline material within the first, second, third and fourth trenches;

the wordline material within the first and second trenches surrounding the first and second outer peripheries of the first and second bridges.

15. The method of claim 14 wherein the semiconductor material is second semiconductor material;

wherein the active regions comprise first semiconductor material;

wherein the intervening regions comprise insulative material;

wherein the forming of the first and second trenches comprises forming the first and second trenches to extend into the first semiconductor material; and

wherein the forming of the third and fourth trenches comprises forming the third and fourth trenches to extend into the insulative material.

16. The method of claim 14 further comprising lining the third and fourth trenches with insulative material prior to forming the wordline material within the third and fourth trenches.

17. The method of claim 14 wherein the third and fourth trenches are formed to be wider than the first and second trenches;

and wherein the forming of the spacers comprises;

forming spacer material within the first, second third and fourth trenches;

the spacer material filling bottom regions of the first and second trenches to thereby form the spacers;

the spacer material forming liners along upper regions of the first and second trenches, and along inner peripheries of the third and fourth trenches; and

etching the spacer material to remove the liners from the first, second, third and fourth trenches while leaving the spacers within the first and second trenches.

18. The method of claim 17 wherein the liners are first liners, wherein the forming of the spacers leaves remaining portions of the first and second trenches over the spacers, and wherein the forming of the bridges comprises:

forming the semiconductor material within the third and fourth trenches, and within the remaining portions of the first and second trenches;

the semiconductor material filling bottom regions of the remaining portions of the first and second trenches to thereby form the bridges;

the semiconductor material forming second liners along upper regions of the remaining portions of the first and second trenches, and along inner peripheries of the third and fourth trenches; and

removing the second liners from the first, second, third and fourth trenches while leaving the bridges within the first and second trenches.

19. The method of claim 18 wherein the forming of the semiconductor material comprises depositing the semiconductor material.

20. The method of claim 18 the semiconductor material is a second semiconductor material;

wherein the active regions comprise a first semiconductor material; and

wherein the forming of the second semiconductor material comprises epitaxial growth of the second semiconductor material from surfaces of the first semiconductor material.

21. The method of claim 14 wherein the semiconductor material is a second semiconductor material;

wherein the active regions comprise a first semiconductor material; and

wherein the first and second trenches subdivide an upper portion of said one of the active regions into three pedestals;

the three pedestals being a first pedestal, a second pedestal and a third pedestal;

the first and second pedestals joining to one another along a bottom surface of the first trench, and the second and third pedestals joining to one another along a bottom surface of the second trench.

22. The method of claim 21 wherein the second semiconductor material comprises a different composition relative to the first semiconductor material.

23. The method of claim 21 wherein the second semiconductor material comprises a same composition as the first semiconductor material.

24. The method of claim 21 wherein the first and second semiconductor materials both comprise silicon.

25. The method of claim 21 further comprising providing dopant within the first, second and third pedestals to form a first source/drain region within the first pedestal, a second source/drain region within the second pedestal and a third source/drain region within the third pedestal.

26. The method of claim 25 further comprising forming a bitline coupled with the second source/drain region, and forming charge-storage devices coupled with the first and third source/drain regions.