Nanosheet transistors on bulk material

• US 10,347,719 B2
• Filed: 07/06/2018
• Issued: 07/09/2019
• Est. Priority Date: 02/13/2017
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Xie, Ruilong, Yamashita, Tenko, Yeh, Chun-Chen
• Primary Examiner(s): Tobergte, Nicholas J
• Application Number:
  US16/028,495
• Publication Number:
  US 20180331179A1
• Time in Patent Office: 368 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.

Claims

1. A semiconductor structure comprising:

a first source/drain located in a first source/drain region;

a second source/drain located in a second source/drain region;

a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region; and

an insulating layer separating the first source drain from a bulk substrate, wherein the bulk substrate has a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface, and wherein the insulating layer is directly on the second horizontal surface and the connecting surface.

2. The semiconductor structure of claim 1, wherein a distance between each of the plurality of nanosheets is about 4 nm and about 10 nm.

3. The semiconductor structure of claim 1, wherein a distance from the first surface of the bulk semiconductor to a bottom surface of the plurality of semiconductor nanosheets is about 50 nm and about 200 nm.

4. The semiconductor structure of claim 1, wherein a portion of the insulating layer is located above the first horizontal surface, and wherein the portion of the insulating layer is substantially perpendicular to the first horizontal surface.

5. The semiconductor structure of claim 4 further comprising:

a gate dielectric layer in direct contact with the plurality of nanosheets and the portion of the insulating layer, wherein the insulating layer is sandwiched by the gate dielectric layer and the second source/drain.

6. The semiconductor structure of claim 1, further comprising:

an insulating layer remnant separating a portion of the first source/drain and a gate of the semiconductor structure.

7. The semiconductor structure of claim 1, further comprising:

a void partially filled with an inter layer dielectric, wherein a horizontal top surface of the void is formed by a horizontal bottom surface of the first source/drain, and a vertical side surface and a horizontal bottom surface are both formed by the insulating layer.

8. A semiconductor structure comprising:

a first source/drain located in a first source/drain region;

a second source/drain located in a second source/drain region;

a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region; and

an insulating layer separating the first source drain from a bulk substrate, wherein the bulk substrate has a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, a third horizontal surface in the bulk substrate, a first connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface, a second connecting surface forming an at least partially vertical connection between the first horizontal surface and the third horizontal surface, and wherein the insulating layer is directly on the first horizontal surface, the second horizontal surface, the third horizontal surface, the first connecting surface and the second connecting surface.

9. The semiconductor structure of claim 8, wherein a distance between each of the plurality of nanosheets is about 4 nm and about 10 nm.

10. The semiconductor structure of claim 8, wherein a distance from the first surface of the bulk semiconductor to a bottom surface of the plurality of semiconductor nanosheets is about 50 nm and about 200 nm.

11. The semiconductor structure of claim 8, wherein a portion of the insulating layer is located above the first horizontal surface, and wherein the portion of the insulating layer is substantially perpendicular to the first horizontal surface.

12. The semiconductor structure of claim 11, further comprising:

a void partially filled with an interlayer dielectric, wherein a horizontal top surface of the void is formed by a horizontal bottom surface of the first source/drain, and a vertical side surface and a horizontal bottom surface are both formed by the insulating layer.