Fin structures and multi-Vt scheme based on tapered fin and method to form

• US 10,347,740 B2
• Filed: 12/02/2016
• Issued: 07/09/2019
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wu, Xusheng, Chi, Min-hwa, Banghart, Edmund Kenneth
• Primary Examiner(s): Kalam, Abul
• Application Number:
  US15/367,366
• Publication Number:
  US 20170084718A1
• Time in Patent Office: 949 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Claims

1. A method comprising:

forming a silicon (Si) fin;

forming a hard mask on a top surface of the Si fin;

forming an oxide layer on opposite sides of the Si fin;

implanting a dopant into the Si fin with a vertical channel implant or a punch-through stop (PTS) vertical implant;

recessing the oxide layer to reveal an active area of the Si fin; and

modifying sidewalls of the active area of the Si fin by etching the sidewalls with plasma Si etching,

wherein the plasma Si etching comprises selectively etching the sidewalls to form multiple levels of verticality of the sidewalls.

2. The method according to claim 1, wherein the forming of the Si fin comprises etching.

3. The method according to claim 1, wherein the recessing of the oxide layer comprises recessing the oxide layer 20 nanometer (nm) to 60 nm to reveal the active area of the Si fin.

4. The method according to claim 1, wherein the recessing the oxide layer comprises recessing with lateral or vertical etching by tuning selectivity.

5. A method comprising:

forming a silicon (Si) fin;

forming a hard mask on a top surface of the Si fin;

forming an oxide layer on opposite sides of the Si fin;

implanting a dopant into the Si fin with a vertical channel implant or a punch-through stop (PTS) vertical implant;

recessing the oxide layer to reveal an active area of the Si fin; and

modifying sidewalls of the active area of the Si fin by etching the sidewalls with plasma Si etching,

wherein the plasma Si etching comprises selectively etching the sidewalls with masking steps to form multiple levels of tapered sidewalls.