Semiconductor device

• US 10,347,763 B2
• Filed: 09/07/2017
• Issued: 07/09/2019
• Est. Priority Date: 03/03/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung Soo, Roh, Dong Hyun, Ryu, Koung Min, Hyun, Sang Jin
• Primary Examiner(s): Fernandes, Errol V
• Application Number:
  US15/697,678
• Publication Number:
  US 20180254338A1
• Time in Patent Office: 670 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

Claims

1. A semiconductor device, comprising:

an active fin extending in a first direction on a substrate;

a device isolation film disposed on the substrate and covering a lower portion of the active fin;

a gate structure extending in a second direction and covering the active fin and the device isolation film, the second direction being perpendicular with respect to the first direction; and

a gate spacer disposed on a side wall of the gate structure,

wherein the gate structure disposed on the device isolation film has upper and lower portions, a width of the lower portion being narrower than a width of the upper portion;

wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure;

wherein an inner side wall of the gate spacer disposed on the device isolation film is disposed to be adjacent to the gate structure, and is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer and totaling an acute angle with respect to a bottom surface of the gate spacer;

wherein the gate spacer includes a first spacer adjacent to the grate structure, and a second spacer disposed on an outer sidewall of the first spacer; and

wherein the first spacer has a structure bent at a boundary of the gate structure and the device isolation film, and a width of the second spacer increases toward the device isolation film.

2. The semiconductor device of claim 1, wherein an outer side wall of the gate spacer disposed on the device isolation film and an upper surface of the substrate are substantially at a right angle with respect to each other.

3. The semiconductor device of claim 1, wherein a width of the gate spacer increases toward an upper surface of the substrate, and wherein the width is widest at a portion in which the gate spacer is in contact with the device isolation film.

4. The semiconductor device of claim 1:

wherein the gate structure disposed on the device isolation film has an inverted trapezoidal cross section; and

wherein the gate spacer disposed on the device isolation film has a trapezoidal cross section.

5. The semiconductor device of claim 1:

wherein the gate structure disposed on the active fin has upper and lower portions, a width of the lower portion being narrower than a width of an upper portion; and

wherein a side wall of the gate structure disposed on the active fin is inclined with a uniform inclination.

6. The semiconductor device of claim 1:

wherein the gate structure includes a gate insulating layer, a first gate electrode layer, and a second gate electrode layer; and

wherein the gate insulating layer includes a high-k insulating material.

7. The semiconductor device of claim 6:

wherein the gate insulating layer on the device isolation film conformally covers an inner side wall of the gate spacer and an upper surface of the device isolation film; and

wherein the first gate electrode layer conformally covers the gate insulating layer.

8. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first active fin disposed on the first region of the substrate;

a first device isolation film covering a lower portion of the first active fin;

a first gate structure disposed on the first active fin and the first device isolation film;

a first gate spacer disposed on a side wall of the first gate structure;

a second active fin disposed on the second region of the substrate;

a second device isolation film covering a lower portion of the second active fin;

a second gate structure disposed on the second active fin and the second device isolation film; and

a second gate spacer disposed on a side wall of the second gate structure,

wherein a side wall of the first gate structure disposed on the first device isolation film forms a first angle with respect to an upper surface of the substrate;

wherein a side wall of the second gate structure disposed on the second device isolation film forms a second angle with respect to an upper surface of the substrate,

wherein the second angle is greater than the first angle;

wherein a difference between the second angle and the first angle is in a range from 3 degrees to 8 degrees;

wherein the first gate spacer includes a first spacer adjacent to the first gate structure, and a second spacer disposed on an outer sidewall of the first spacer; and

wherein the first spacer has a structure bent at a boundary of the gate structure and the device isolation film, and a width of the second spacer increases toward the device isolation film.

9. The semiconductor device of claim 8, wherein the difference between the second angle and the first angle is in a range from 4 degrees to 7 degrees.

10. The semiconductor device of claim 8:

wherein the first gate spacer has a first side wall and a second side wall opposing each other, and a bottom surface located between the first side wall and the second side wall;

wherein the first side wall adjacent to a side wall of the first gate structure forms an acute angle with respect to the bottom surface; and

wherein the second side wall and the bottom surface are substantially at a right angle with respect to each other.

11. The semiconductor device of claim 8, wherein the substrate further includes a third region and wherein the semiconductor device further comprises:

a third active fin disposed on the third region of the substrate;

a third device isolation film covering a lower portion of the third active fin;

a third gate structure disposed on the third active fin and the third device isolation film; and

a third gate spacer disposed on a side wall of the third gate structure,

wherein a side wall of the third gate structure disposed on the third device isolation film forms a third angle with respect to an upper surface of the substrate; and

wherein the third angle is greater than the second angle.

12. The semiconductor device of claim 11, wherein the third gate spacer has upper and lower portions, a width of the lower portion narrower than a width of the upper portion.

13. A semiconductor device comprising:

an active fin extended in a first direction on a substrate;

a device isolation film disposed on the substrate and covering a lower portion of the active fin;

a gate structure extended in a second direction and covering the active fin and the device isolation film, the second direction being perpendicular with respect to the first direction; and

a gate spacer disposed on a side wall of the gate structure,

wherein an inner side wall of the gate spacer disposed on the device isolation film is disposed to be adjacent to the gate structure, and is inclined at a uniform inclination from a point higher than half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with respect to a bottom surface of the gate spacer;

wherein an outer side wall of the gate spacer disposed on the device isolation film and an upper surface of the substrate are substantially at a right angle with respect to each other;

wherein the gate spacer includes a first spacer adjacent to the gate structure, and a second spacer disposed on an outer sidewall of the first spacers; and

wherein the first spacer has a structure bent at a boundary of the gate structure and the device isolation film, and a width of the second spacer increases toward the device isolation film.

14. The semiconductor device of claim 13, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than half of a height of the gate structure to a bottom of the gate structure.

15. The semiconductor device of claim 13, wherein a width of a lower portion of the gate spacer disposed on the device isolation film is narrower wider than a width of a lower portion of the gate spacer disposed on the active fin.