Resistive random access memory and fabrication method thereof

• US 10,347,833 B2
• Filed: 09/13/2016
• Issued: 07/09/2019
• Est. Priority Date: 09/29/2015
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Xiao, Lihong
• Primary Examiner(s): Tran, Tony
• Application Number:
  US15/263,918
• Publication Number:
  US 20170092854A1
• Time in Patent Office: 1,029 Days
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/041 Modification of the switching material, e.g. post-treatment, doping
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/801 Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/828 Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

The present disclosure provides resistive random access memory and fabrication methods thereof. An exemplary fabrication method of the resistive random access memory includes providing a substrate; forming a bottom electrode on the substrate; forming a resistance switching layer on the bottom electrode; forming a barrier on the resistance switching layer; and forming a top electrode on the barrier layer. The barrier is used to prevent atoms in the top electrode from diffusing into the resistance switching layer.

Claims

1. A method for fabricating a resistive random access memory, comprising:

providing a substrate;

forming a bottom electrode on the substrate;

forming a resistance switching layer on the bottom electrode, the resistance switching layer including nanoparticles that are amorphous;

after forming the resistance switching layer, performing a plasma treatment process on a surface of the resistance switching layer;

forming a barrier layer on the resistance switching layer after performing the plasma treatment process on the surface of the resistance switching layer to cause the barrier layer to have a uniform thickness; and

forming a top electrode on the barrier layer, the top electrode having a double-layer stacked structure,

wherein the barrier layer is used to prevent atoms in the top electrode from diffusing into the resistance switching layer, and

wherein forming the top electrode comprises;

forming a first top electrode on the barrier layer; and

forming a second top electrode made of a metal nitride covering the first top electrode made of a metal material, a resistivity of the first top electrode being lower than a resistivity of the second top electrode, wherein the first top electrode made of the metal material is sandwiched by the second top electrode made of a metal nitride and the barrier layer;

wherein;

the resistance switching layer is made of amorphous silicon;

wherein;

the barrier layer is made of one of silicon oxide and silicon nitride; and

wherein;

a thickness of the barrier layer is in a range of approximately 10Å

-30Å

.

2. The method according to claim 1, wherein:

the barrier layer is formed by a plasma-enhanced vapor deposition (PECVD) process.

3. The method according to claim 2, when the barrier layer is made of silicon oxide, wherein:

gases of the PECVD process include SiH₄, N₂O, N₂, and He;

a flow rate of SiH₄ is in a range of approximately 10 sccm-50 sccm;

a flow rate of N₂O is in range of approximately 20 sccm-100 sccm;

a flow rate of N₂ is in a range of approximately 10000 sccm-20000 sccm;

a flow rate of He is in a range of approximately 10000 sccm-20000 sccm;

a pressure of a reaction chamber of the PECVD process is in a range of approximately 2 Torr-5 Torr;

a high-frequency power is in a range of approximately 50 W-100 W;

a low-frequency power is in a range of approximately 10 W-50 W; and

a temperature of the PECVD process is in a range of approximately 200°

C.-400°

C.

4. The method according to claim 2, when the barrier layer is made of silicon nitride, wherein:

gases of the PECVD process include SiH₄, NH₃, and N₂;

a flow rate of SiH₄ is in a range of approximately 10 sccm-50 sccm;

a flow rate of NH₃ is in range of approximately 20 sccm-100 sccm;

a flow rate of N₂ is in a range of approximately 10000 sccm-20000 sccm;

a pressure of a reaction chamber of the PECVD process is in a range of approximately 2 Torr-5 Torr;

a high-frequency power is in a range of approximately 50 W-100 W;

a low-frequency power is in a range of approximately 10 W-50 W; and

a temperature of the PECVD process is in a range of approximately 200°

C.-400°

C.

5. The method according to claim 2, wherein:

a deposition rate of the barrier layer is in a range of approximately 2 Å

/s-5 Å

/s.

6. The method according to claim 1, wherein:

the first top electrode is made of Al; and

the second top electrode is made of TiN.

7. The method according to claim 1, wherein:

a thickness of the resistance switching layer is in a range of approximately 30Å

-50Å

.

8. The method according to claim 1, wherein

the barrier layer is configured to prevent a bonding process between the first top electrode and the resistance switching layer.

9. The method according to claim 1, wherein

the first top electrode having a desired crystallinity at the interface between the first top electrode and the resistance switching layer.

10. The method according to claim 1, wherein

a top interconnect layer is formed on the top electrode.

11. The method according to claim 10, wherein

the top interconnect layer is a metal layer, of a logic back end of line structure.

12. The method according to claim 1, wherein:

the first top electrode is made of Cu; and

the second top electrode is made of W, Ti, or Mo.

13. The method according to claim 1, wherein:

the barrier layer is formed by a low-pressure chemical vapor deposition process or an atomic layer deposition process.

14. The method according to claim 1, wherein:

the substrate is a bottom metal interconnect layer,

the bottom metal interconnect layer includes a bottom dielectric layer.

15. The method according to claim 1, wherein:

the barrier layer is sandwiched by the first top electrode and the resistance switching layer.

16. A method for fabricating a resistive random access memory, comprising:

providing a substrate;

forming a bottom electrode on the substrate;

forming a resistance switching layer on the bottom electrode;

after forming the resistance switching layer and before forming a barrier layer, performing a plasma treatment process on a surface of the resistance switching layer, wherein;

a gas of the plasma treatment process includes N₂;

a flow rate of the gas of the plasma treatment process is in a range of approximately 100 sccm-1000 sccm;

a high-frequency power of the plasma treatment process is in a range of approximately 100 W-1000 W;

a low-frequency power of the plasma treatment process is in a range of approximately 10 W-100 W;

a pressure of a reaction chamber of the plasma treatment process is in a range of approximately 1 Torr-10 Torr;

a temperature of the plasma treatment process is in a range of approximately 200°

C.-400°

C.; and

time of the plasma treatment process is in a range of approximately 5 s-20 s;

forming the barrier layer on the resistance switching layer; and

forming a top electrode on the barrier layer, the top electrode having a double-layer stacked structure,

wherein the barrier layer is used to prevent atoms in the top electrode from diffusing into the resistance switching layer, and

wherein forming the top electrode comprises;

forming a first top electrode on the barrier layer; and

forming a second top electrode on the first top electrode, a resistivity of the first top electrode being lower than a resistivity of the second top electrode.