Low power switched-capacitor comparator

• US 10,348,283 B1
• Filed: 02/22/2018
• Issued: 07/09/2019
• Est. Priority Date: 02/22/2018
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Sonntag, Jeffrey L., Miroslav, Svajda, Wei, Dazhi
• Primary Examiner(s): Skibinski, Tomi
• Application Number:
  US15/902,798
• Time in Patent Office: 502 Days
• Field of Search: 327 77
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/155 using semiconductor devices only
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

A voltage converter includes a comparator that continuously monitors an output voltage of the voltage converter. The comparator includes a first comparator core utilizing first and second switched capacitors and a second comparator core using third and fourth switched capacitors. The first comparator core is powered down or in a refresh mode while the second comparator core is monitoring the output voltage. The second comparator core is powered down or in the refresh mode while the first comparator core is monitoring the output voltage. The first and second switched capacitors are configured in series with an amplifier stage of the first comparator core while the first comparator core is monitoring the output voltage. The refresh mode charges the first (third) and second (fourth) switched capacitors to a scaled version of the output voltage and a reference voltage less an offset voltage, respectively.

Claims

1. A method comprising:

monitoring an output voltage using a first comparator core and a second comparator core by operating the first comparator core and the second comparator core such that when the first comparator core is monitoring the output voltage, the second comparator core is powered off or the second comparator core is being refreshed and when the second comparator core is monitoring the output voltage the first comparator core is powered off or the second comparator core is being refreshed;

refreshing the first comparator core by causing a first sample capacitor to store a first scaled version of the output voltage and causing a first reference capacitor to store a first voltage; and

refreshing the second comparator core by causing a second sample capacitor to store a second scaled version of the output voltage and causing a second reference capacitor to store a second voltage.

2. The method as recited in claim 1 further comprising resetting the first comparator core responsive to the first comparator core asserting a low voltage indication thereby indicating the output voltage is lower than a target voltage represented by the first scaled version of the output voltage and the first voltage in series.

3. The method as recited in claim 1, further comprising:

storing the first scaled version by coupling a first node of the first sample capacitor to the output voltage and a second node of the first sample capacitor to a reduced version of the output voltage to thereby store the first scaled version of the output voltage across the first sample capacitor; and

storing the first voltage by storing a first voltage difference between a reference voltage and a first offset voltage fed back from an amplifier stage of the first comparator core.

4. The method as recited in claim 1, further comprising:

during the refreshing of the first comparator core, opening a first switch to isolate the first sample capacitor from the first reference capacitor; and

closing the first switch to cause the first sample capacitor and the first reference capacitor to be in series when the first comparator core is monitoring the output voltage.

5. The method as recited in claim 1, further comprising:

keeping a charging circuit used during refresh powered off when refresh is not being performed.

6. The method as recited in claim 1, further comprising:

storing the first scaled version by coupling a first node of the first sample capacitor to the output voltage and a second node of the first sample capacitor to a reduced version of the output voltage to thereby store the first scaled version of the output voltage across the first sample capacitor.

7. The method as recited in claim 1 further comprising:

monitoring the output voltage for an out of range condition using a third comparator core when the first comparator core is monitoring the output voltage; and

monitoring the output voltage for the out of range condition using a fourth comparator core when the second comparator core is monitoring the output voltage.

8. The method as recited in claim 1 further comprising resetting the first comparator core responsive to the first comparator core asserting a low voltage indicator thereby indicating the output voltage is lower than a threshold voltage.

9. A method comprising:

monitoring an output voltage using a first comparator core and a second comparator core by operating the first comparator core and the second comparator core such that when the first comparator core is monitoring the output voltage, the second comparator core is powered off or the second comparator core is being refreshed and when the second comparator core is monitoring the output voltage the first comparator core is powered off or the second comparator core is being refreshed; and

adjusting a first bias current supplied to an amplifier of the first comparator core while the second comparator core is monitoring the output voltage without affecting a second bias current being supplied to the second comparator core.

10. A comparator comprising:

a first comparator core and a second comparator core;

control logic configured to maintain the first comparator core powered down or in a refresh mode to refresh the first comparator core while the second comparator core is monitoring an output voltage; and

the control logic being further configured to maintain the second comparator core powered down or in the refresh mode while the first comparator core is monitoring the output voltage;

wherein the first comparator core further includes,

a first sample capacitor to store a first scaled version of the output voltage;

a first reference capacitor to store a first voltage difference between a reference voltage and a first offset voltage fed back from an amplifier stage of the first comparator core;

a first switch to isolate the first sample capacitor from the first reference capacitor during the refresh mode;

wherein the first sample capacitor and the first reference capacitor are coupled in series through the first switch while the first comparator core is monitoring the output voltage.

11. The comparator recited in claim 10 wherein one or more amplifier stages of the first comparator core is reset responsive to the first comparator core asserting a low voltage indicator thereby indicating the output voltage is lower than a threshold voltage.

12. The comparator as recited in claim 10, wherein during refresh of the first comparator core a first node of the first sample capacitor is coupled to the output voltage and a second node of the first sample capacitor is coupled to a reduced version of the output voltage to thereby store the first scaled version of the output voltage across the first sample capacitor.

13. The comparator as recited in claim 10, further comprising:

a charging circuit used to charge the first reference capacitor and the first sample capacitor during refresh; and

wherein the charging circuit is powered off when no refresh is occurring in the comparator.

14. The comparator as recited in claim 10, further comprising

a bias current generating circuit configured to supply an adjusted first bias current to the first comparator core during refresh of the first comparator core without supplying the adjusted first bias current supplied to the second comparator core.

15. A voltage converter comprising:

a comparator to continuously monitor an output voltage of the voltage converter, the comparator including,

a first comparator core utilizing first and second switched capacitors;

a second comparator core using third and fourth switched capacitors;

wherein the first comparator core is powered down or in a refresh mode to refresh the first comparator core while the second comparator core is monitoring the output voltage; and

wherein the second comparator core is powered down or in the refresh mode to refresh the second comparator core while the first comparator core is monitoring the output voltage, the first and second switched capacitors being configured in series with an amplifier stage of the first comparator core while the first comparator core is monitoring the output voltage.

16. The voltage converter as recited in claim 15 further comprising:

wherein the first switched capacitor is isolated from the second switched capacitor while the first and second switched capacitors are being independently refreshed and the first switched capacitor is configured in series with the second switched capacitor while the first comparator core is monitoring the output voltage.

17. The voltage converter as recited in claim 15 further comprising:

a charging circuit selectively coupled to the first and second switched capacitors, the charging circuit being powered off when not being used for refresh.

18. The voltage converter as recited in claim 15 further comprising:

a fast refresh cycle in which the first and second comparator cores are refreshed back to back.

19. The voltage converter as recited in claim 15 where the third switched capacitor is configured in series with the fourth switched capacitor while the second comparator core is monitoring the output voltage.

20. The voltage converter as recited in claim 15 wherein the first comparator core is configured to assert a low voltage indication responsive to the output voltage being lower than a target voltage when the first comparator core is monitoring the output voltage, the target voltage being represented by a voltage across the first and second switched capacitors in series.