Memory decision feedback equalizer bias level generation

• US 10,348,534 B1
• Filed: 01/08/2018
• Issued: 07/09/2019
• Est. Priority Date: 01/08/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sreeramaneni, Raghukiran, Taylor, Jennifer E.
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US15/864,972
• Publication Number:
  US 20190215198A1
• Time in Patent Office: 547 Days
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04L 25/021 Estimation of channel covariance
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.

Claims

1. A device, comprising:

a receiver comprising;

a first input configured to receive a reference signal;

a second input configured to receive an adjustment signal; and

a third input configured to receive a feedback signal, wherein the receiver is configured to generate a set of output signals based on the reference signal, the adjustment signal, and the feedback signal;

an operational amplifier comprising;

a fourth input configured to receive a first output signal of the set of output signals from the receiver;

a fifth input configured to receive a second output signal of the set of output signals from the receiver, wherein the operational amplifier is configured to generate the feedback signal based on the first output signal and the second output signal; and

a first output coupled to;

the third input of the receiver; and

an adjustment circuit of a decision feedback equalizer configured to transmit adjustment signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream, wherein the first output is configured to transmit the feedback signal to the third input and the adjustment circuit.

2. The device of claim 1, wherein the first input is configured to receive the reference signal as a threshold value for determination of whether a bit corresponds to a logical low value or a logical high value.

3. The device of claim 1, wherein the second input is configured to receive the adjustment signal as a modified version of the reference signal.

4. The device of claim 3, wherein the modified version of the reference signal comprises a correction factor related to a desired level of correction of the adjustment signal.

5. The device of claim 1, wherein the receiver emulates the behavior of an amplifying device, a summer, or any combination, thereof of the decision feedback equalizer.

6. The device of claim 1, wherein the operational amplifier generates the feedback signal based on a difference between the first output signal and the second output signal.

7. The device of claim 1, wherein the operational amplifier comprises a differential operational amplifier.

8. The device of claim 1, wherein the receiver is configured to adjust the set of output signals to match one another at a first level.

9. The device of claim 8, wherein the receiver is configured to readjust the set of output signals to match one another at a second level in response to a change in operating conditions affecting the decision feedback equalizer.

10. The device of claim 9, wherein the operating conditions comprise process, voltage, or temperature changes affecting operation of the decision feedback equalizer.

11. A device configured to generate a set of bias levels comprising:

a receiver comprising a plurality of inputs each configured to receive a respective one of a reference signal, an adjustment signal, a first feedback signal, and a second feedback signal and a plurality of outputs configured to transmit a set of output signals based on the reference signal, the adjustment signal, the first feedback signal, and the second feedback signal;

an operational amplifier comprising at least one input configured to receive the set of output signals from the receiver, wherein the operational amplifier is configured to generate the first feedback signal based on the set of output signals; and

a current mirror configured to generate the second feedback signal, a first bias level of the set of bias levels, and a second bias level of the set of bias levels based on the first feedback signal, wherein the current mirror comprises at least one output configured to transmit the first bias level and the second bias level to a decision feedback equalizer configured to transmit adjustment signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

12. The device of claim 11, wherein the first bias level and the second bias level comprise a voltage value having a common value.

13. The device of claim 11, wherein the receiver is configured to adjust the set of output signals based on the first feedback signal and the second feedback signal.

14. The device of claim 11, comprising a first controllable current source configured to provide a current to adjust a value of a first adjustment signal of the adjustment signals.

15. The device of claim 14, wherein the first controllable current source receives the first bias level as a control input value.

16. The device of claim 14, comprising a second controllable current source configured to provide a second current to adjust the value of the first adjustment signal of the adjustment signals.

17. The device of claim 16, wherein the second controllable current source receives the second bias level as a control input value.

18. A device, comprising:

a selection circuit configured to generate a bias level, wherein the selection circuit comprises a receiver, an operational amplifier, and a feedback loop configured to couple an output of the operational amplifier to an input of the receiver to adjust the bias level in response to a change in operating conditions affecting a decision feedback equalizer;

a combinational circuit coupled to the selection circuit and configured to generate a distortion correction factor used to offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal, wherein the combinational circuit comprises a first combinational circuit, wherein the first combinational circuit comprises a digital adder as a portion of the decision feedback equalizer; and

a data latch coupled to the combinational circuit and configured to receive the correction signal.