Facilitating transaction completion subsequent to repeated aborts of the transaction

• US 10,353,759 B2
• Filed: 05/15/2018
• Issued: 07/16/2019
• Est. Priority Date: 06/15/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Belmar, Brenton F., Jacobi, Christian, Philley, Randall W., Slegel, Timothy J.
• Primary Examiner(s): Pham, Tuan A
• Application Number:
  US15/979,610
• Publication Number:
  US 20180260263A1
• Time in Patent Office: 427 Days
• Field of Search: None
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 16/2365 Ensuring data consistency and integrity
• CPC Class Codes: G06F 9/466 Transaction processing

Abstract

Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

Claims

1. A computer program product for facilitating processing within a computing environment, said computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising;

tracking, by a processor of the computing environment, a number of times a transaction executing within the processor aborts, the tracking employing a counter within the processor to track the number of aborts;

determining whether the transaction has successfully completed, and based on the transaction successfully completing, automatically resetting the counter to a selected value;

based on the transaction aborting and there being an interrupt associated with the transaction, automatically setting the counter to a predefined value;

based on the transaction aborting, determining whether the transaction is to be re-executed, wherein the determining whether the transaction is to be re-executed comprises determining whether the counter has reached a threshold number of aborts for the transaction, and based on the counter not reaching the threshold number of aborts, determining whether an action is to be taken to facilitate successful completion of the transaction on re-execution and setting a program instruction address to a transaction begin instruction to re-execute the transaction; and

re-executing the transaction to facilitate successful completion of the transaction, based on determining the transaction is to be re-executed, wherein processing within the computing environment is facilitated.

2. The computer program product of claim 1, wherein the interrupt is to be presented for the transaction, based on the counter reaching the threshold number of aborts for the transaction.

3. The computer program product of claim 1, wherein the transaction is a constrained transaction having a plurality of restrictions associated therewith, and wherein the re-executing the transaction is via a transaction begin constrained instruction.

4. The computer program product of claim 1, wherein based on the counter not reaching the threshold number of aborts, incrementing the counter.

5. The computer program product of claim 1, wherein the method further comprises:

selecting one or more actions based on the determining indicating an action is to be performed; and

performing the selected one or more actions.

6. The computer program product of claim 5, wherein the one or more actions are selected from a group consisting of:

disabling branch prediction, disabling speculative instruction fetching, disabling super-scalar dispatching, disabling out-of-order execution, fetching cache misses exclusively, and executing a single instruction through an instruction pipeline.

7. The computer program product of claim 5, wherein the selecting comprises choosing an action based on one or more of a value of the counter and a reason for the abort.

8. The computer program product of claim 1, wherein the automatically setting the counter is based on determining the abort is due to an interruption.

9. A computer system for facilitating processing within a computing environment, said computer system comprising:

a memory; and

a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising;

tracking, by the processor, a number of times a transaction executing within the processor aborts, the tracking employing a counter within the processor to track the number of aborts;

determining whether the transaction has successfully completed, and based on the transaction successfully completing, automatically resetting the counter to a selected value;

based on the transaction aborting and there being an interrupt associated with the transaction, automatically setting the counter to a predefined value;

based on the transaction aborting, determining whether the transaction is to be re-executed, wherein the determining whether the transaction is to be re-executed comprises determining whether the counter has reached a threshold number of aborts for the transaction, and based on the counter not reaching the threshold number of aborts, determining whether an action is to be taken to facilitate successful completion of the transaction on re-execution and setting a program instruction address to a transaction begin instruction to re-execute the transaction; and

re-executing the transaction to facilitate successful completion of the transaction, based on determining the transaction is to be re-executed, wherein processing within the computing environment is facilitated.

10. The computer system of claim 9, wherein the automatically setting the counter is based on determining the abort is due to an interruption.

11. The computer system of claim 9, wherein based on the counter not reaching the threshold number of aborts, incrementing the counter.

12. The computer system of claim 11, wherein the interrupt is to be presented for the transaction, based on the counter reaching the threshold number of aborts for the transaction, and wherein the transaction is a constrained transaction having a plurality of restrictions associated therewith, and wherein the re-executing the transaction is via a transaction begin constrained instruction.

13. The computer system of claim 9, wherein the method further comprises:

selecting one or more actions based on the determining indicating an action is to be performed; and

performing the selected one or more actions, wherein the one or more actions are selected from a group consisting of;

disabling branch prediction, disabling speculative instruction fetching, disabling super-scalar dispatching, disabling out-of-order execution, fetching cache misses exclusively, and executing a single instruction through an instruction pipeline.

14. The computer system of claim 13, wherein the selecting comprises choosing an action based on one or more of a value of the counter and a reason for the abort.

15. A computer-implemented method of facilitating processing within a computing environment, said computer-implemented method comprising:

tracking, by a processor of the computing environment, a number of times a transaction executing within the processor aborts, the tracking employing a counter within the processor to track the number of aborts;

determining whether the transaction has successfully completed, and based on the transaction successfully completing, automatically resetting the counter to a selected value;

based on the transaction aborting and there being an interrupt associated with the transaction, automatically setting the counter to a predefined value;

based on the transaction aborting, determining whether the transaction is to be re-executed, wherein the determining whether the transaction is to be re-executed comprises determining whether the counter has reached a threshold number of aborts for the transaction, and based on the counter not reaching the threshold number of aborts, determining whether an action is to be taken to facilitate successful completion of the transaction on re-execution and setting a program instruction address to a transaction begin instruction to re-execute the transaction; and

re-executing the transaction to facilitate successful completion of the transaction, based on determining the transaction is to be re-executed, wherein processing within the computing environment is facilitated.

16. The computer-implemented method of claim 15, wherein based on the counter not reaching the threshold number of aborts, incrementing the counter.

17. The computer-implemented method of claim 16, wherein the interrupt is to be presented for the transaction based on the counter reaching the threshold number of aborts for the transaction, and wherein the transaction is a constrained transaction having a plurality of restrictions associated therewith, and wherein the re-executing the transaction is via a transaction begin constrained instruction.

18. The computer-implemented method of claim 15, further comprising:

selecting one or more actions based on the determining indicating an action is to be performed; and

performing the selected one or more actions, wherein the one or more actions are selected from a group consisting of;

disabling branch prediction, disabling speculative instruction fetching, disabling super-scalar dispatching, disabling out-of-order execution, fetching cache misses exclusively, and executing a single instruction through an instruction pipeline.

19. The computer-implemented method of claim 18, wherein the selecting comprises choosing an action based on one or more of a value of the counter and a reason for the abort.

20. The computer-implemented method of claim 15, wherein the automatically setting the counter is based on determining the abort is due to an interruption.