Ferroelectric memory cells

• US 10,354,712 B2
• Filed: 08/17/2018
• Issued: 07/16/2019
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derner, Scott J., Kawamura, Christopher J.
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US16/104,709
• Publication Number:
  US 20190005999A1
• Time in Patent Office: 333 Days
• Field of Search: 365145, 365149, 365190
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2253 Address circuits or decoders
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 11/2259 Cell access
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

Claims

1. An apparatus, comprising:

a first capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to a plate line structure;

a second capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to the plate line structure;

a first transistor vertically displaced relative to the first capacitor and coupled to the second plate of the first capacitor; and

a second transistor vertically displaced relative to the second capacitor and coupled to the second plate of the second capacitor, wherein the first plate of the first capacitor and the first plate of the second capacitor are inner plates configured to fit into a respective outer plate.

2. The apparatus of claim 1, wherein the second plate of the first capacitor is a first container-shaped outer plate configured to fit the first plate of the first capacitor, and wherein the second plate of the second capacitor is a second container-shaped outer plate configured to fit the second plate of second capacitor.

3. The apparatus of claim 1, further comprising:

a first digit line coupled to a first source/drain region of the first transistor; and

a second digit line coupled to a second source/drain region of the second transistor.

4. The apparatus of claim 3, wherein the first transistor includes a first semiconductor pillar extending upwardly from the first digit line, the first semiconductor pillar including the first source/drain region of the first transistor.

5. The apparatus of claim 4, wherein the first semiconductor pillar further includes a third source/drain region of the first transistor, the third source/drain region coupled to the second plate of the first capacitor.

6. The apparatus of claim 4, wherein the second semiconductor pillar further includes a fourth source/drain region of the second transistor, the fourth source/drain region coupled to the second plate of the second capacitor.

7. The apparatus of claim 3, wherein the second transistor includes a second semiconductor pillar extending downwardly from the second digit line, the second semiconductor pillar including the second source/drain region of the second transistor.

8. The apparatus of claim 1 wherein the first transistor and the second transistor are vertically displaced relative to one another.

9. The apparatus of claim 1 wherein the first and second transistors include respective gates coupled to respective word lines.

10. An apparatus comprising:

a first capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to a plate line structure;

a second capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to the plate line structure;

a first transistor vertically displaced relative to the first capacitor and coupled to the second plate of the first capacitor; and

a second transistor vertically displaced relative to the second capacitor and coupled to the second plate of the second capacitor, wherein the first plate of the first capacitor and the first plate of the second capacitor have a different composition than a composition of the plate line structure.

11. An apparatus, comprising:

a first memory cell;

a second memory cell; and

a plate line structure coupled to the first memory cell and the second memory cell;

wherein each memory cell comprises;

a first transistor;

a first ferroelectric capacitor including a ferroelectric material, coupled to the first transistor and vertically displaced relative to the first transistor;

a second transistor; and

a second ferroelectric capacitor coupled to the second transistor and vertically displaced relative to the second transistor, wherein a plate of the first ferroelectric capacitor and a plate of the second ferroelectric capacitor have a different composition than a composition of the plate line structure.

12. The apparatus of claim 11,

wherein the plate line structure is shared by the first and second memory cells.

13. The apparatus of claim 12 wherein the first and second memory cells are laterally displaced relative to one another.

14. The apparatus of claim 11, further comprising:

a first digit line shared by the first and second memory cells; and

a second digit line shared by the first and second memory cells.

15. A method of accessing a memory cell, comprising:

activating first and second transistors of the memory cell;

applying a voltage to a plate line coupled to first and second ferroelectric capacitors, the first ferroelectric capacitor coupled to the first transistor and vertically displaced relative to the first transistor and the second ferroelectric capacitor coupled to the second transistor and vertically displaced relative to the second transistor;

comparing a first voltage developed at a first digit line coupled to the first ferroelectric capacitor to a second voltage developed at a second digit line coupled to the second ferroelectric capacitor; and

changing a voltage in the first digit line and the second digit line based on applying the voltage to the plate line coupled to the first and second ferroelectric capacitors.

16. The method of claim 15, further comprising:

determining a stored state of the memory cell based the comparison of the first voltage developed at the first digit line coupled to the first ferroelectric capacitor to the second voltage developed at the second digit line coupled to the second ferroelectric capacitor.

17. The method of claim 16, wherein determining the stored state of the memory cell comprises:

detecting a high logic state when the first voltage developed at the first digit line is higher than a reference voltage; and

detecting a low logic state when the first voltage developed at the first digit line is lower than the reference voltage.

18. The method of claim 15, wherein comparing the first voltage developed at the first digit line coupled to the first ferroelectric capacitor to the second voltage developed at the second digit line coupled to the second ferroelectric capacitor comprises amplifying a difference between the first voltage developed at the first digit line and the second voltage developed at the second digit line.