Systems and methods for reducing standby power in floating body memory devices
First Claim
1. A semiconductor memory array configured for reducing standby power, said array comprising:
- a plurality of floating body memory cells configured to store charge representative of data; and
at least two floating body cells serially connected to form a reference cell;
wherein current conducted through said at least one of said plurality of floating body memory cells is reduced to a fraction of said current when passing through said reference cell.
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Accused Products
Abstract
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
336 Citations
12 Claims
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1. A semiconductor memory array configured for reducing standby power, said array comprising:
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a plurality of floating body memory cells configured to store charge representative of data; and at least two floating body cells serially connected to form a reference cell; wherein current conducted through said at least one of said plurality of floating body memory cells is reduced to a fraction of said current when passing through said reference cell. - View Dependent Claims (2, 3, 7, 8, 9)
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4. A semiconductor memory array configured for reducing standby power, said array comprising:
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a plurality of floating body memory cells configured to store charge representative of data; and at least two more of said floating body memory cells interconnected by a segmented source line to form a reference cell. - View Dependent Claims (5, 6, 10, 11, 12)
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Specification