Non-halogen etching of silicon-containing materials

• US 10,354,889 B2
• Filed: 07/17/2017
• Issued: 07/16/2019
• Est. Priority Date: 07/17/2017
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Choi, Tom, Pandit, Mandar B., Ling, Mang-Mang, Ingle, Nitin K.
• Primary Examiner(s): Pham, Thomas T
• Application Number:
  US15/651,607
• Publication Number:
  US 20190019690A1
• Time in Patent Office: 729 Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32138 pre- or post-treatments, e.g. anti-corrosion processes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide.

Claims

1. An etching method comprising:

forming a plasma consisting of an inert precursor within a processing region of a semiconductor processing chamber;

passivating, with the plasma consisting of the inert precursor, an exposed region of an oxygen-containing material, wherein the oxygen-containing material extends about a feature formed on a semiconductor substrate contained within the processing region to limit exposure of the feature to the plasma;

forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber;

directing plasma effluents of the hydrogen-containing precursor towards an exposed silicon-containing material on the semiconductor substrate, wherein the plasma effluents of the hydrogen-containing precursor are directed with a DC bias; and

anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, wherein the plasma effluents selectively etch silicon relative to the oxygen-containing material.

2. The etching method of claim 1, wherein the inert precursor is helium.

3. The etching method of claim 1, wherein the plasma consisting of the inert precursor are directed towards the oxygen-containing material with a DC bias.

4. The etching method of claim 1, wherein a pressure within the semiconductor processing chamber while forming the plasma consisting of the inert precursor and during the passivating is maintained below about 50 mTorr.

5. The etching method of claim 1, wherein the feature formed on the semiconductor substrate comprises a silicon fin.

6. The etching method of claim 1, wherein the DC bias directing the plasma effluents of the hydrogen-containing precursor is below about 250 W.

7. The etching method of claim 1, wherein a pressure within the semiconductor processing chamber while forming the plasma of the hydrogen-containing precursor and during the anisotropic etching is maintained below about 2 Torr.

8. The etching method of claim 1, further comprising repeating the etching method in at least one additional cycle.

9. The etching method of claim 1, wherein the anisotropic etching of the exposed silicon-containing material comprises anisotropically etching with ions of the hydrogen-containing precursor.

10. The etching method of claim 1, wherein a temperature within the semiconductor processing chamber is maintained below 150°

C.

11. The etching method of claim 1, further comprising implanting the exposed silicon-containing material on the semiconductor substrate with the plasma effluents of the hydrogen-containing precursor prior to forming the plasma from the inert gas precursor and passivating the exposed region of the oxygen-containing material.

12. An etching method comprising:

forming a first plasma consisting of an inert precursor, wherein forming the first plasma consisting of the inert precursor comprises applying a first DC bias to a processing region in a semiconductor processing chamber;

contacting an exposed region of an oxygen-containing material with the first plasma consisting of the inert precursor, wherein the oxygen-containing material covers a feature formed on a semiconductor substrate within the processing region, wherein the first plasma consisting of the inert precursor passivates the exposed region of the oxygen-containing material and limit exposure of the feature to the first plasma;

forming a second plasma of an hydrogen-containing precursor, wherein forming a second plasma comprises applying a second DC bias to the semiconductor processing chamber; and

directing plasma effluents of the hydrogen-containing precursor towards an exposed silicon-containing material on the semiconductor substrate; and

anisotropically etching, with the plasma effluents of the hydrogen-containing precursor, the exposed silicon-containing material, wherein the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to the oxygen-containing material.

13. The etching method of claim 12, wherein the inert precursor is helium.

14. The etching method of claim 12, wherein a pressure within the semiconductor processing chamber while forming the first plasma consisting of the inert precursor and during the passivating is maintained below about 50 mTorr.

15. The etching method of claim 12, wherein the feature formed on the semiconductor substrate comprises a silicon fin.

16. The etching method of claim 12, wherein the second DC bias directing the plasma effluents of the hydrogen-containing precursor is below about 250 W.

17. The etching method of claim 12, wherein a pressure within the semiconductor processing chamber while forming the plasma of the hydrogen-containing precursor and during the anisotropic etching is maintained below about 2 Torr.

18. The etching method of claim 12, wherein the anisotropic etching of the exposed silicon-containing material comprises anisotropically etching with ions of the hydrogen-containing precursor.

19. The etching method of claim 12, wherein the exposed silicon-containing material is a dummy gate.

20. The etching method of claim 12, further comprising repeating the etching method in at least one additional cycle.