Semiconductor memory device and structure

• US 10,354,995 B2
• Filed: 03/16/2018
• Issued: 07/16/2019
• Est. Priority Date: 10/12/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Beinglass, Israel, Wurman, Zeev
• Primary Examiner(s): Williams, Alexander O
• Application Number:
  US15/922,913
• Publication Number:
  US 20180204835A1
• Time in Patent Office: 487 Days
• Field of Search: 257762
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/11898 : Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 : oriented parallel to a substrate
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/458 : for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66272 : Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 : using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78639 : with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78645 : with multiple gate
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the device to a second external device.

Claims

1. A semiconductor device, the device comprising:

a first layer comprising a first memory cell, said first memory cell comprising a first transistor;

a second layer comprising a second memory cell, said second memory cell comprising a second transistor;

a periphery layer comprising a memory peripherals transistor, said periphery layer is disposed underneath said first layer;

a memory comprising at least said first memory cell and said second memory cell,

wherein said second memory cell overlays said first memory cell,

wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and

wherein a peripherals circuit comprises said memory peripherals transistor and said peripherals circuit controls said memory;

a first plurality of external connections underlying said periphery layer, said first plurality of external connections comprises connections from said device to a first external device; and

a second plurality of external connections overlying said second layer, said second plurality of external connections comprises connections from said device to a second external device.

2. The semiconductor device according to claim 1, further comprising:

a NAND flash memory,

wherein said NAND flash memory comprises said second memory cell.

3. The semiconductor device according to claim 1,

wherein said first transistor comprises a transistor channel, and

wherein said transistor channel comprises polysilicon.

4. The semiconductor device according to claim 1,

wherein said first transistor comprises a source, channel and drain, and

wherein said source, said channel and said drain have the same dopant type.

5. The semiconductor device according to claim 1, further comprising:

an interconnect layer disposed between said memory peripherals transistor and said first transistor,

wherein said interconnect layer comprises tungsten.

6. The semiconductor device according to claim 1,

wherein said first plurality of external connections comprises a through silicon via (TSV).

7. The semiconductor device according to claim 1,

wherein said first transistor and said memory peripherals transistor have a misalignment to each other of less than 200 nm.

13. The semiconductor device according to claim 1, further comprising:

a staircase structure,

wherein said staircase structure comprises a connection from said peripherals circuit to said second memory cell.

8. A semiconductor device, the device comprising:

a first layer comprising a first memory cell, said first memory cell comprising a first transistor;

a second layer comprising a second memory cell, said second memory cell comprising a second transistor;

a periphery layer comprising memory peripherals transistor, said periphery layer is disposed underneath said first layer;

a memory comprising at least said first memory cell and said second memory cell,

wherein said second memory cell overlays said first memory cell,

wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and

wherein said peripherals circuit comprises said memory peripherals transistor and said peripherals circuit controls said memory;

a first plurality of external connections underlying said periphery layer, said first plurality of external connections comprises connections from said device to a first external device; and

a second plurality of external connections overlying said second layer, said second plurality of external connections comprises connections from said device to a second external device,

wherein said first plurality of external connections comprises a through silicon via (TSV).

9. The semiconductor device according to claim 8, further comprising:

a NAND flash memory,

wherein said NAND flash memory comprises said second memory cell.

10. The semiconductor device according to claim 8,

wherein said first transistor comprises a transistor channel, and

wherein said transistor channel comprises polysilicon.

11. The semiconductor device according to claim 8,

wherein said first transistor comprises a source, channel and drain, and

wherein said source, said channel and said drain have the same dopant type.

12. The semiconductor device according to claim 8, further comprising:

an interconnect layer disposed between said memory peripherals transistor and said first transistor,

wherein said interconnect layer comprises tungsten.

14. The semiconductor device according to claim 8,

wherein said first transistor and said memory peripherals transistor have a misalignment to each other of less than 200 nm.

15. A semiconductor device, the device comprising:

a first layer comprising a first memory cell, said first memory cell comprising a first transistor;

a second layer comprising a second memory cell, said second memory cell comprising a second transistor;

a periphery layer comprising memory peripherals transistor, said periphery layer is disposed underneath said first layer;

a memory comprising at least said first memory cell and said second memory cell,

wherein said second memory cell overlays said first memory cell,

wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and

wherein a peripherals circuit comprises said memory peripherals transistor and said peripherals circuit controls said memory, and

wherein said memory peripherals transistor comprises a single crystal channel;

a first plurality of external connections underlying said periphery layer, said first plurality of external connections comprises connections from said device to a first external device; and

a second plurality of external connections overlying said second layer, said second plurality of external connections comprises connections from said device to a second external device,

wherein said first plurality of external connections comprises a through silicon via (TSV).

16. The semiconductor device according to claim 15, further comprising:

a NAND flash memory,

wherein said NAND flash memory comprises said second memory cell.

17. The semiconductor device according to claim 15,

wherein said first transistor comprises a transistor channel, and

wherein said transistor channel comprises polysilicon.

18. The semiconductor device according to claim 15,

wherein said first transistor comprises a source, channel and drain, and

wherein said source, said channel and said drain have the same dopant type.

19. The semiconductor device according to claim 15, further comprising:

an interconnect layer disposed between said memory peripherals transistor and said first transistor,

wherein said interconnect layer comprises tungsten.

20. The semiconductor device according to claim 15,

wherein said first transistor and said memory peripherals transistor have a misalignment to each other of less than 200 nm.