Semiconductor memory device and structure
First Claim
1. A semiconductor device, the device comprising:
- a first layer comprising a first memory cell, said first memory cell comprising a first transistor;
a second layer comprising a second memory cell, said second memory cell comprising a second transistor;
a periphery layer comprising a memory peripherals transistor, said periphery layer is disposed underneath said first layer;
a memory comprising at least said first memory cell and said second memory cell,wherein said second memory cell overlays said first memory cell,wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, andwherein a peripherals circuit comprises said memory peripherals transistor and said peripherals circuit controls said memory;
a first plurality of external connections underlying said periphery layer, said first plurality of external connections comprises connections from said device to a first external device; and
a second plurality of external connections overlying said second layer, said second plurality of external connections comprises connections from said device to a second external device.
1 Assignment
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Accused Products
Abstract
A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the device to a second external device.
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Citations
20 Claims
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1. A semiconductor device, the device comprising:
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a first layer comprising a first memory cell, said first memory cell comprising a first transistor; a second layer comprising a second memory cell, said second memory cell comprising a second transistor; a periphery layer comprising a memory peripherals transistor, said periphery layer is disposed underneath said first layer; a memory comprising at least said first memory cell and said second memory cell, wherein said second memory cell overlays said first memory cell, wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and wherein a peripherals circuit comprises said memory peripherals transistor and said peripherals circuit controls said memory; a first plurality of external connections underlying said periphery layer, said first plurality of external connections comprises connections from said device to a first external device; and a second plurality of external connections overlying said second layer, said second plurality of external connections comprises connections from said device to a second external device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 13)
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8. A semiconductor device, the device comprising:
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a first layer comprising a first memory cell, said first memory cell comprising a first transistor; a second layer comprising a second memory cell, said second memory cell comprising a second transistor; a periphery layer comprising memory peripherals transistor, said periphery layer is disposed underneath said first layer; a memory comprising at least said first memory cell and said second memory cell, wherein said second memory cell overlays said first memory cell, wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and wherein said peripherals circuit comprises said memory peripherals transistor and said peripherals circuit controls said memory; a first plurality of external connections underlying said periphery layer, said first plurality of external connections comprises connections from said device to a first external device; and a second plurality of external connections overlying said second layer, said second plurality of external connections comprises connections from said device to a second external device, wherein said first plurality of external connections comprises a through silicon via (TSV). - View Dependent Claims (9, 10, 11, 12, 14)
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15. A semiconductor device, the device comprising:
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a first layer comprising a first memory cell, said first memory cell comprising a first transistor; a second layer comprising a second memory cell, said second memory cell comprising a second transistor; a periphery layer comprising memory peripherals transistor, said periphery layer is disposed underneath said first layer; a memory comprising at least said first memory cell and said second memory cell, wherein said second memory cell overlays said first memory cell, wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and wherein a peripherals circuit comprises said memory peripherals transistor and said peripherals circuit controls said memory, and wherein said memory peripherals transistor comprises a single crystal channel; a first plurality of external connections underlying said periphery layer, said first plurality of external connections comprises connections from said device to a first external device; and a second plurality of external connections overlying said second layer, said second plurality of external connections comprises connections from said device to a second external device, wherein said first plurality of external connections comprises a through silicon via (TSV). - View Dependent Claims (16, 17, 18, 19, 20)
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Specification