Method for manufacturing semiconductor device with replacement gates

• US 10,354,997 B2
• Filed: 04/28/2017
• Issued: 07/16/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fan, Chia-Sheng, Young, Bao-Ru, Hsieh, Tung-Heng
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/581,565
• Publication Number:
  US 20180315752A1
• Time in Patent Office: 809 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not

Abstract

A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Claims

1. A method comprising:

forming a first fin and a second fin on a substrate;

forming a dummy gate material over the first fin and the second fin;

patterning the dummy gate material to form a dummy gate structure;

forming gate spacers adjacent the dummy gate structure over the first fin and the second fin;

after patterning the dummy gate material and forming the gate spacers, forming an opening in the dummy gate structure between the first fin and the second fin;

forming a sacrificial oxide on sidewalls of the dummy gate structure in the opening, the sacrificial oxide being different than the gate spacers;

filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate structure in the opening;

removing the dummy gate structure and the sacrificial oxide;

depositing a gate dielectric layer over the first fin, over the second fin, and over the insulation material;

forming a metal over the gate dielectric layer; and

planarizing top surfaces of the metal, the gate dielectric layer, and the insulation material to form a first gate electrode over the first fin and a second gate electrode over the second fin.

2. The method of claim 1, wherein the filling the insulation material between the sacrificial oxide on the sidewalls comprises forming silicon nitride between the sacrificial oxide on the sidewalls.

3. The method of claim 1, wherein the forming the sacrificial oxide comprises oxidizing the sidewalls of the dummy gate structure.

4. The method of claim 3, wherein the oxidizing the sidewalls of the dummy gate structure comprises oxidizing the sidewalls at a temperature of from 800°

C. to 1100°

C.

5. The method of claim 3, wherein the oxidizing the sidewalls of the dummy gate structure comprises oxidizing the sidewalls for a time period of from 10 seconds to 20 seconds.

6. The method of claim 3, wherein the oxidizing the sidewalls of the dummy gate structure comprises oxidizing the sidewalls to a thickness of from 28 Å

to 56 Å

.

7. The method of claim 1, wherein the forming the opening in the dummy gate structure comprises:

forming the opening having a first width proximate the substrate and a second width distal the substrate, the second width greater than the first width.

8. The method of claim 7, wherein the opening has a convex shape in a plan view.

9. The method of claim 1, wherein the forming the opening in the dummy gate structure comprises:

forming the opening having a first width proximate each of the gate spacers in a plan view, and a second width distal the gate spacers in the plan view, the first width greater than the second width.

10. The method of claim 1, wherein the planarizing the top surfaces of the metal, the gate dielectric layer, and the insulation material comprises:

forming remaining portions of the metal between the first fin and the insulation material, and between the second fin and the insulation material.

11. The method of claim 1, further comprising:

forming source/drain regions in the first fin and the second fin, the source/drain regions being adjacent the dummy gate structure; and

forming an inter-layer dielectric (ILD) over the source/drain regions, the insulation material being different than the ILD.

12. A method comprising:

forming a first fin in a first region of a substrate and a second fin in a second region of the substrate;

forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin;

forming a dummy gate material over the first fin and the second fin;

depositing gate spacers along sides of the dummy gate material;

after depositing the gate spacers, forming an opening in the dummy gate material, the opening exposing the first isolation region and sidewalls of the gate spacers;

forming a sacrificial oxide in the opening on sidewalls of the dummy gate material;

filling an insulating material in the opening between the sacrificial oxide on the sidewalls of the dummy gate material;

removing remaining portions of the dummy gate material and the sacrificial oxide; and

forming replacement gates over the first fin and the second fin.

13. The method of claim 12, wherein the forming the replacement gates comprises:

depositing a first gate dielectric on the first fin and a second gate dielectric on the second fin; and

forming a first metal on the first gate dielectric and a second metal on the second gate dielectric.

14. The method of claim 13, wherein the first gate dielectric extends along a first side of the insulating material, and the second gate dielectric extends along a second side of the insulating material.

15. The method of claim 12, wherein the insulating material is formed on the sidewalls of the gate spacers, the sacrificial oxide being different than the gate spacers.

16. The method of claim 15, wherein the insulating material comprises:

first portions adjacent the gate spacers, the first portions having first widths; and

a second portion between the first portions, the second portion having a second width less than the first widths.

17. A method comprising:

forming a plurality of first fins in a first region of a substrate;

forming a plurality of second fins in a second region of the substrate;

depositing a dummy gate on the first fins and the second fins;

depositing gate spacers along sides of the dummy gate;

forming an inter-layer dielectric (ILD) adjacent the gate spacers;

after forming the gate spacers and the ILD, etching an opening in the dummy gate between the first fins and the second fins;

oxidizing sidewalls of remaining portions of the dummy gate exposed to the opening;

forming a first isolation region along the oxidized sidewalls of the dummy gate in the opening, the gate spacers contacting sidewalls of the first isolation region and the ILD;

removing the remaining portions of the dummy gate;

after removing the remaining portions of the dummy gate, depositing a first gate dielectric on the first fins and along a first sidewall of the first isolation region;

after removing the remaining portions of the dummy gate, depositing a second gate dielectric on second first fins and along a second sidewall of the first isolation region; and

forming a first metal on the first gate dielectric and a second metal on the second gate dielectric.

18. The method of claim 17, further comprising:

forming a second isolation region on the substrate between the first fins and the second fins, the first isolation region being formed on the second isolation region.

19. The method of claim 18, wherein the first gate dielectric and the second gate dielectric are spaced apart a first distance proximate the second isolation region and are spaced apart a second distance distal the second isolation region, the first distance being less than the second distance.

20. The method of claim 17, wherein after the etching the opening in the dummy gate, the opening has a first width proximate the gate spacers and a second width distal the gate spacers, the first width greater than the second width.