Thin film transistor structure and method for manufacturing same

• US 10,355,021 B2
• Filed: 11/08/2017
• Issued: 07/16/2019
• Est. Priority Date: 09/21/2017
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Original Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
• Inventors: Yu, Mingjue, Im, Jangsoon
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US15/578,256
• Publication Number:
  US 20190088684A1
• Time in Patent Office: 615 Days
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

A thin film transistor structure is provided with a glass substrate, a buffer layer, a metal oxide semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a source metal layer, a drain metal layer, and a protective layer. A shielding metal layer is disposed between the glass substrate and the buffer layer, the gate insulating layer has a shielding metal layer contact hole passing through the gate insulating layer and the buffer layer, and the gate metal layer connects with the shielding metal layer through the shielding metal layer contact hole.

Claims

1. A thin film transistor structure, comprising:

a glass substrate,

a buffer layer disposed on the glass substrate;

a metal oxide semiconductor layer disposed on the buffer layer, and configured to define a position of an active drive area of the thin film transistor structure through the metal oxide semiconductor layer, wherein the metal oxide semiconductor layer comprises a source electrode area, a drain electrode area, and a channel area;

a gate insulating layer disposed on the metal oxide semiconductor layer to separate the metal oxide semiconductor layer from a gate metal layer;

wherein the gate metal layer is disposed on the gate insulating layer;

an interlayer insulating layer disposed on the gate metal layer for performing a planarization treatment on the glass substrate having the gate metal layer, wherein the interlayer insulating layer has a source contact hole and a drain contact hole therein;

a source metal layer disposed on the interlayer insulating layer, and configured to connect with the source electrode area of the metal oxide semiconductor layer through the source contact hole;

a drain metal layer disposed on the interlayer insulating layer, and configured to connect with the drain electrode area of the metal oxide semiconductor layer through the drain contact hole; and

a protective layer disposed on the interlayer insulating layer having the source metal layer and the drain metal layer;

wherein a shielding metal layer is disposed between the glass substrate and the buffer layer,

the gate insulating layer has a shielding metal layer contact hole passing through the gate insulating layer and the buffer layer, and the gate metal layer connects with the shielding metal layer through the shielding metal layer contact hole;

a projection area of the shielding metal layer on a plane of the glass substrate covers a projection area of the metal oxide semiconductor layer on the plane of the glass substrate;

the projection area of the shielding metal layer on the plane of the glass substrate covers an entire area of the thin film transistor structure corresponding to the plane of the glass substrate;

the shielding metal layer has a thickness ranging from 500 Å

to 2000 Å

;

the buffer layer has a thickness ranging from 1000 Å

to 5000 Å

;

the metal oxide semiconductor layer has a thickness ranging from 100 Å

to 1000 Å

;

the gate insulating layer has a thickness ranging from 1000 Å

to 3000 Å

;

the interlayer insulating layer has a thickness ranging from 2000 Å

to 10000 Å

;

the source metal layer has a thickness ranging from 2000 Å

to 8000 Å

;

the drain metal layer has a thickness ranging from 2000 Å

to 8000 Å

;

the protective layer has a thickness from 1000 Å

to 5000 Å

;

a material of the shielding metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the buffer layer is at least one of silica and silicon nitride;

a material of the metal oxide semiconductor layer is at least one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide;

a material of the gate insulating layer is at least one of silica and silicon nitride;

a material of the gate metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the source metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the drain metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the interlayer insulating layer is at least one of silica and silicon nitride; and

a material of the protective layer is at least one of silica and silicon nitride.

2. A thin film transistor structure, comprising:

a glass substrate;

a buffer layer disposed on the glass substrate;

a metal oxide semiconductor layer disposed on the buffer layer, and configured to define a position of an active drive area of the thin film transistor structure through the metal oxide semiconductor layer, wherein the metal oxide semiconductor layer comprises a source electrode area, a drain electrode area, and a channel area;

a gate insulating layer disposed on the metal oxide semiconductor layer to separate the metal oxide semiconductor layer from a gate metal layer;

wherein the gate metal layer is disposed on the gate insulating layer;

an interlayer insulating layer disposed on the glass substrate having the gate metal layer for performing a planarization treatment on the glass substrate having the gate metal layer, wherein the interlayer insulating layer has a source contact hole and a drain contact hole therein;

a source metal layer disposed on the interlayer insulating layer, and configured to connect with the source electrode area of the metal oxide semiconductor layer through the source contact hole;

a drain metal layer disposed on the interlayer insulating layer, and configured to connect with the drain electrode area of the metal oxide semiconductor layer through the drain contact hole; and

a protective layer disposed on the interlayer insulating layer having the source metal layer and the drain metal layer;

wherein a shielding metal layer is disposed between the glass substrate and the buffer layer,

the gate insulating layer has a shielding metal layer contact hole passing through the gate insulating layer and the buffer layer, and the gate metal layer connects with the shielding metal layer through the shielding metal layer contact hole,

wherein a projection area of the shielding metal layer on a plane of the glass substrate covers a projection area of the metal oxide semiconductor layer on the plane of the glass substrate, and the projection area of the shielding metal layer on the plane of the glass substrate covers an entire area of the thin film transistor structure corresponding to the plane of the glass substrate.

3. The thin film transistor structure according to claim 2, wherein the shielding metal layer has a thickness ranging from 500 Å

to 2000 Å

;

the buffer layer has a thickness ranging from 1000 Å

to 5000 Å

;

the metal oxide semiconductor layer has a thickness ranging from 100 Å

to 1000 Å

;

the gate insulating layer has a thickness ranging from 1000 Å

to 3000 Å

;

the interlayer insulating layer has a thickness ranging from 2000 Å

to 10000 Å

;

the source metal layer has a thickness ranging from 2000 Å

to 8000 Å

;

the drain metal layer has a thickness ranging from 2000 Å

to 8000 Å

; and

the protective layer has a thickness ranging from 1000 Å

to 5000 Å

.

4. The thin film transistor structure according to claim 2, wherein

a material of the shielding metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the gate metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the source metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal; and

a material of the drain metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal.

5. The thin film transistor structure according to claim 2, wherein a material of the buffer layer is at least one of silica and silicon nitride;

a material of the gate insulating layer is at least one of silica and silicon nitride;

a material of the interlayer insulating layer is at least one of silica and silicon nitride; and

a material of the protective layer is at least one of silica and silicon nitride.

6. The thin film transistor structure according to claim 2, wherein a material of the metal oxide semiconductor layer is at least one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide.

7. A method for manufacturing a thin film transistor structure, comprising steps of:

providing a glass substrate;

depositing a shielding metal layer on the glass substrate, and patterning the shielding metal layer;

depositing a buffer layer on the shielding metal layer;

depositing a metal oxide semiconductor layer on the buffer layer, and patterning the metal oxide semiconductor layer to define a position of an active area of the thin film transistor structure;

wherein the metal oxide semiconductor layer comprises a source electrode area, a drain electrode area, and a channel area;

depositing a gate insulating layer on the metal oxide semiconductor layer, and the gate insulating layer is provided with a shielding metal layer contact hole passing through the gate insulating layer and the buffer layer;

depositing a gate metal layer on the gate insulating layer, and patterning the gate metal layer;

wherein the gate metal layer connects with the shielding metal layer through the shielding metal layer contact hole;

depositing an interlayer insulating layer on the gate metal layer, and the interlayer insulating layer is provided with a source contact hole and a drain contact hole;

applying a source metal layer and a drain metal layer on the interlayer insulating layer, wherein the source metal layer connects with the source electrode area of the metal oxide semiconductor layer through the source contact hole; and

the drain metal layer connect with the drain electrode area of the metal oxide semiconductor layer through the drain contact hole; and

depositing a protective layer on the source metal layer and the drain metal layer,

wherein a projection area of the shielding metal layer on a plane of the glass substrate covers a projection area of the metal oxide semiconductor layer on the plane of the glass substrate, and the projection area of the shielding metal layer on the plane of the glass substrate covers an entire area of the thin film transistor structure corresponding to the plane of the glass substrate.

8. The method for manufacturing a thin film transistor structure according to claim 7, wherein the shielding metal layer has a thickness ranging from 500 Å

to 2000 Å

;

the buffer layer has a thickness ranging from 1000 Å

to 5000 Å

;

the metal oxide semiconductor layer has a thickness ranging from 100 Å

to 1000 Å

;

the gate insulating layer has a thickness ranging from 1000 Å

to 3000 Å

;

the interlayer insulating layer has a thickness ranging from 2000 Å

to 10000 Å

;

the source metal layer has a thickness ranging from 2000 Å

to 8000 Å

;

the drain metal layer has a thickness ranging from 2000 Å

to 8000 Å

; and

the protective layer has a thickness ranging from 1000 Å

to 5000 Å

.

9. The method for manufacturing a thin film transistor structure according to claim 7, wherein a material of the shielding metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the gate metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal;

a material of the source metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal; and

a material of the drain metal layer is at least one of a molybdenum metal, an aluminum metal, a copper metal, and a titanium metal.

10. The method for manufacturing a thin film transistor structure according to claim 7, wherein a material of the buffer layer is at least one of silica and silicon nitride;

a material of the gate insulating layer is at least one of silica and silicon nitride;

a material of the interlayer insulating layer is at least one of silica and silicon nitride; and

a material of the protective layer is at least one of silica and silicon nitride.

11. The method for manufacturing a thin film transistor structure according to claim 7, wherein a material of the metal oxide semiconductor layer is at least one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium tin oxide.