Semiconductor device including a transistor with a gate dielectric having a variable thickness

• US 10,355,087 B2
• Filed: 03/07/2016
• Issued: 07/16/2019
• Est. Priority Date: 10/02/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Vielemeyer, Martin, Meiser, Andreas, Schloesser, Till, Hirler, Franz, Poelzl, Martin
• Primary Examiner(s): Armand, Marc Anthony
• Assistant Examiner(s): Tang, Sue
• Application Number:
  US15/062,370
• Publication Number:
  US 20160190256A1
• Time in Patent Office: 1,226 Days
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/2822 with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Claims

1. A semiconductor device comprising a transistor in a semiconductor substrate having a main surface, the transistor comprising:

a source region;

a drain region laterally spaced apart from the source region;

a channel region and a drift zone each being laterally disposed between the source and drain regions;

a gate trench formed in the main surface of the semiconductor substrate;

an electrically conductive gate electrode formed in the gate trench;

a gate dielectric formed in the gate trench and electrically insulating the gate electrode from the semiconductor substrate,

wherein the gate trench comprises;

first, second, third and fourth sidewalls and a bottom surface, the first sidewall extending though and facing the source region, the second sidewall extending through and facing the drift zone, and third and fourth sidewalls each extending through and facing the channel region and each extending from the first sidewall to the second sidewall,

wherein the second sidewall is laterally spaced apart from the drain region by a portion of the drift zone, and

wherein a first thickness of the gate dielectric as measured between the gate electrode and the second sidewall is greater than a second thickness of the gate dielectric as measured between the gate electrode and the first sidewall.

2. The semiconductor device of claim 1, wherein the gate electrode comprises a first end that faces the first sidewall, a second end that faces the second sidewall, and wherein the gate electrode is elongated in a length direction that extends between the first and second ends.

3. The semiconductor device of claim 2, wherein the gate electrode comprises third and fourth side faces that are parallel to one another and each extend from the first end to the second end, wherein a thickness of the gate electrode as measured between the third and fourth side faces is substantially uniform throughout a length of the gate electrode, the length of the gate electrode being measured between the first and second ends.

4. The semiconductor device of claim 1, wherein a thickness of the gate dielectric as measured between the gate electrode and the third sidewall is substantially identical to the second thickness.

5. The semiconductor device of claim 1, wherein the gate electrode has an asymmetric geometry from a plan-view perspective.

6. The semiconductor device of claim 5, wherein the gate electrode comprises a first end that faces the first sidewall, a second end that faces the second sidewall, and third and fourth side faces that are parallel to one another and each extend from the first end to the second end, and wherein from the plan-view perspective the first end is completely curved from the third face to the fourth face and the second end is completely linear from the third face to the fourth face.

7. The semiconductor device of claim 6, wherein a portion of the gate dielectric between the first sidewall of the gate trench and the first end of the gate electrode is C-shaped and has the second thickness throughout the C-shape.

8. A semiconductor device comprising a transistor in a semiconductor substrate having a main surface, the transistor comprising:

a source region;

a drain region laterally spaced apart from the source region;

a channel region and a drift zone each being laterally disposed between the source and drain regions;

a plurality of gate trenches formed in the main surface of the semiconductor substrate,

an electrically conductive electrode formed in each of the gate trenches,

a gate dielectric formed in each of the gate trenches, the gate dielectric electrically insulating each gate electrode from the semiconductor substrate;

a plurality of field plate trenches formed in the main surface of the semiconductor substrate;

an electrically conductive field plate formed in each of the field plate trenches;

a gate dielectric formed in each of the gate trenches, the gate dielectric electrically insulating each field plate from the semiconductor substrate,

wherein each of the gate trenches extend in a first lateral direction from the source region through the channel region to reach the drift zone,

wherein each of the field plate trenches are disposed within the drift zone and laterally separated from each of the gate trenches in the first lateral direction,

wherein a pitch of the gate trenches is smaller than a pitch of the field plate trenches, the pitch of the gate trenches and field plate trenches being measured in a second lateral direction of the semiconductor device, the second lateral direction being perpendicular to the first lateral direction and parallel to the main surface.

9. The semiconductor device of claim 8, wherein each gate trench comprises:

first, second, third and fourth sidewalls and a bottom surface, the first sidewall extending though and facing the source region, the second sidewall extending through the drift zone and facing the drain region, and third and fourth sidewalls each extending through and facing the channel region and each extending from the first sidewall to the second sidewall, and

wherein, for at least one of the gate trenches;

a first thickness of the gate dielectric as measured between the gate electrode and any one of the first sidewall, the second sidewall, the third sidewall, the fourth sidewall, or the bottom surface is different from a second thickness of the gate dielectric as measured between the gate dielectric and any different one of the first sidewall, the second sidewall, the third sidewall, the fourth sidewall, or the bottom surface.

10. The semiconductor device of claim 9, wherein the first thickness is measured between the gate electrode and the second sidewall, and wherein the second thickness is measured between the gate electrode and any one of:

the first sidewall, the third sidewall, or the fourth sidewall.