3D semiconductor device with stacked memory

• US 10,355,121 B2
• Filed: 10/07/2017
• Issued: 07/16/2019
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Widjaja, Yuniarto
• Primary Examiner(s): Lam, David
• Application Number:
  US15/727,592
• Publication Number:
  US 20180033881A1
• Time in Patent Office: 647 Days
• Field of Search: 365 51, 36518518, 365 72, 257 499, 257774, 257401, 257E23145
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device, the device including: a first stratum including memory periphery circuits; a second stratum including an array of first memory cells, where the first stratum is overlaid by the second stratum; a third stratum including an array of second memory cells, where the second stratum is overlaid by the third stratum, where the first memory cells include a plurality of first polysilicon structures and the second memory cells include a plurality of second polysilicon structures, and where at least one of the first memory cells is self-aligned to at least one of the second memory cells.

Claims

1. A 3D semiconductor device, the device comprising:

a first level comprising a single crystal layer, a plurality of first transistors and at least one metal layer,

wherein said at least one metal layer comprises interconnects between said first transistors forming memory peripheral circuits;

a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors and a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors;

a third level overlaying said second level, said third level comprising a plurality of third transistors and a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors;

polysilicon pillars,

wherein at least one of said second transistors comprises a first channel region and at least one of said third transistors comprises a second channel region,

wherein a portion of at least one of said polysilicon pillars is in direct contact with said first channel region and said second channel region,

wherein said memory peripheral circuits comprise a plurality of decoders,

wherein at least one of said first memory cells at least partially overlays at least one of said decoders; and

a staircase structure,

wherein said staircase structure comprises a portion of connections from said memory peripheral circuits to at least one of said memory cells.

2. The 3D semiconductor device according to claim 1,

wherein said memory peripheral circuits control at least a portion of said plurality of second memory cells.

3. The 3D semiconductor device according to claim 1,

wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following the same lithography step.

4. The 3D semiconductor device according to claim 1,

wherein said second transistors are aligned to said first transistors with less than 40 nm misalignment.

5. The 3D semiconductor device according to claim 1,

wherein said first memory cells are controlled thru a plurality of memory control lines, and

wherein said third level comprises at least one of said memory control lines.

6. The 3D semiconductor device according to claim 1,

wherein said memory peripheral circuits comprise tungsten wiring.

7. The 3D semiconductor device according to claim 1, further comprising:

a fourth level overlaying said third level,

wherein said fourth level comprises a plurality of memory control circuits.

8. A 3D semiconductor device, the device comprising:

a first level comprising a single crystal layer, a plurality of first transistors and at least one metal layer,

wherein said at least one metal layer comprises interconnects between said first transistors forming memory peripheral circuits;

a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors and a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors;

a third level overlaying said second level, said third level comprising a plurality of third transistors and a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors; and

polysilicon pillars,

wherein at least one of said second transistors comprises a first channel region and at least one of said third transistors comprises a second channel region,

wherein a portion of at least one of said polysilicon pillars is in direct contact with said first channel region and said second channel region,

wherein said memory peripheral circuits comprise a plurality of decoders, and

wherein at least one of said first memory cells at least partially overlays at least one of said decoders.

9. The 3D semiconductor device according to claim 8, further comprising:

a staircase structure,

wherein said staircase structure comprises a portion of connections from said memory periphery circuits to at least one of said memory cells.

10. The 3D semiconductor device according to claim 8,

wherein said second transistors are aligned to said first transistors with less than 40 nm misalignment.

11. The 3D semiconductor device according to claim 8,

wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following the same lithography step.

12. The 3D semiconductor device according to claim 8,

wherein transport of control signals to said first memory cells and said second memory cells comprises a plurality of word-lines and a plurality of bit-lines.

13. The 3D semiconductor device according to claim 8,

wherein said first memory cells are controlled thru a plurality of memory control lines, and

wherein said third level comprises at least one of said memory control lines.

14. The 3D semiconductor device according to claim 8, further comprising:

a fourth level overlaying said third level,

wherein said fourth level comprises memory control circuits.

15. A 3D semiconductor device, the device comprising:

a first level comprising a single crystal layer, a plurality of first transistors and at least one metal layer,

wherein said at least one metal layer comprises interconnects between said first transistors forming memory peripheral circuits;

a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors and a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors;

a third level overlaying said second level, said third level comprising a plurality of third transistors and a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors; and

polysilicon pillars,

wherein at least one of said second transistors comprises a first channel region and at least one of said third transistors comprises a second channel region, and

wherein a portion of at least one of said polysilicon pillars is in direct contact with said first channel region and said second channel region.

16. The 3D semiconductor device according to claim 15,

wherein said memory peripheral circuits control at least a portion of said plurality of second memory cells.

17. The 3D semiconductor device according to claim 15,

wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following the same lithography step.

18. The 3D semiconductor device according to claim 15,

wherein said second transistors are aligned to said first transistors with less than 40 nm misalignment.

19. The 3D semiconductor device according to claim 15, further comprising:

a staircase structure,

wherein said staircase structure comprises a portion of connections from said memory periphery circuits to at least one of said memory cells.

20. The 3D semiconductor device according to claim 15, further comprising:

a fourth level overlaying said third level,

wherein said fourth level comprises a plurality of memory control circuits.