Silicon-carbide trench gate MOSFETs and methods of manufacture

• US 10,355,123 B2
• Filed: 12/29/2017
• Issued: 07/16/2019
• Est. Priority Date: 12/26/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Konstantinov, Andrei
• Primary Examiner(s): Reames, Matthew L
• Application Number:
  US15/858,406
• Publication Number:
  US 20180145168A1
• Time in Patent Office: 564 Days
• CPC Class Codes: H01L 21/0455 Making n or p doped regions or layers, e.g. using diffusion
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 21/047 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/8083 : Vertical transistors SIT H01L29/7722

Abstract

In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Claims

1. A method for producing a semiconductor device, the method comprising:

forming a drift region of a first conductivity type in a silicon-carbide (SiC) substrate of the first conductivity type, the drift region being formed on a front side of the SiC substrate, a back side of the SiC substrate including a drain region;

forming a shielding body region of a second conductivity type in the drift region;

forming a source region of the first conductivity type in the shielding body region;

forming a gate trench in the SiC substrate, the gate trench having a depth that is greater than a depth of the source region and less than a depth of the shielding body region;

forming a gate dielectric on a sidewall of the gate trench and a bottom surface of the gate trench, the gate dielectric on the sidewall of the gate trench defining a first interface with the shielding body region, the gate dielectric on the bottom surface of the gate trench defining a second interface with the shielding body region;

forming a gate electrode on the gate dielectric; and

forming a lateral channel region of the first conductivity type, the lateral channel region being disposed in the shielding body region and along the second interface.

2. The method of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. The method of claim 1, wherein forming the lateral channel region includes performing a donor ion implant.

4. The method of claim 1, further comprising:

forming a sub-contact implant region of the second conductivity type in the shielding body region, the sub-contact implant region being disposed adjacent to the source region, the source region being disposed between the sub-contact implant region and the gate trench; and

forming a contact layer on at least a portion of the sub-contact implant region and on at least a portion of the source region, the contact layer establishing a first ohmic contact with the sub-contact implant region and a second ohmic contact with the source region.

5. The method of claim 1, further comprising forming a threshold control region of the second conductivity type in the shielding body region, the threshold control region being disposed below the source region and having a depth that is less than the depth of the shielding body region, the gate dielectric on the sidewall of the gate trench further defining an interface with the threshold control region.

6. The method of claim 1, wherein:

the sidewall of the gate trench defines an angle of greater than 90 degrees with the bottom surface of the gate trench; and

the lateral channel region is further disposed, in the shielding body region, along at least a portion of the first interface.

7. The method of claim 1, wherein the sidewall of the gate trench is spaced a first distance from the shielding body region, the first distance being less than or equal to a second distance, the second distance being a lateral width from a vertical edge of the shielding body region to a vertical edge of a zero-bias depletion region of the semiconductor device.

8. A method for producing a semiconductor device, the method comprising:

forming a drift region of a first conductivity type on a silicon-carbide (SiC) substrate of the first conductivity type;

forming a junction field-effect transistor (JFET) channel region of the first conductivity type on the drift region;

forming a shielding body region of a second conductivity type in the JFET channel region;

forming a channel stopper layer of the second conductivity type on the shielding body region;

forming a source region of the first conductivity type on the channel stopper layer;

forming a gate trench extending through the source region and the channel stopper layer, the gate trench terminating in the JFET channel region and having a sidewall and a bottom surface;

forming a built-in channel of the first conductivity type below the gate trench, the built-in channel having a sidewall portion disposed along at least a portion of the sidewall of the gate trench and a lateral portion disposed along at least a portion of the bottom surface of the gate trench, the built-in channel having a doping concentration that is different than a doping concentration of the JFET channel region;

forming a gate dielectric having a sidewall portion disposed on the sidewall of the gate trench and a lateral portion disposed on the bottom surface of the trench, the lateral portion of the gate dielectric having a thickness that is greater than or equal to two times a thickness of the sidewall portion of the gate dielectric; and

forming a gate electrode on the gate dielectric.

9. The method of claim 8, wherein a doping concentration of the channel stopper layer is greater than a doping concentration of the shielding body region.

10. The method of claim 8, wherein a doping concentration of the lateral portion of the built-in channel is greater than a doping concentration of the sidewall portion of the built-in channel.

11. The method of claim 8, wherein the first conductivity type is n-type and the second conductivity type is p-type.

12. The method of claim 8, wherein the built-in channel continuously extends from the channel stopper layer, through the shielding body region and into the JFET channel region.

13. The method of claim 8, further comprising:

forming a sub-contact implant region of the second conductivity type in the channel stopper layer, the sub-contact implant region being disposed adjacent to the source region, the source region being disposed between the sub-contact implant region and the gate trench; and

forming a contact layer on at least a portion of the sub-contact implant region and on at least a portion of the source region, the contact layer establishing a first ohmic contact with the sub-contact implant region and a second ohmic contact with the source region.

14. The method of claim 8, wherein:

the sidewall portion of the gate dielectric is disposed, within the gate trench, on the source region, on the channel stopper layer and on at least a portion of the sidewall portion of the built-in channel; and

the lateral portion of the gate dielectric is disposed on the lateral portion of the built-in channel.

15. The method of claim 8, wherein the gate trench is a first trench, the method further comprising:

forming a second trench extending through the source region and the channel stopper layer, the second trench terminating in the shielding body region;

forming a sub-contact implant region of the second conductivity type in the shielding body region;

forming a linking implant of the first conductivity type, the linking implant extending from the sub-contact implant region to the source region, the linking implant having a lateral portion and a vertical portion; and

forming a contact layer on at least a portion of the sub-contact implant region and on at least a portion of the linking implant, the contact layer establishing a first ohmic contact with the sub-contact implant region and a second ohmic contact with the source region via the linking implant.

16. The method of claim 8, wherein forming the shielding body region includes forming a first shielding body region, the method further comprising forming a second shielding body region on the first shielding body region, the second shielding body region being disposed in an epitaxial layer of the first conductivity type that is disposed between the JFET channel region and the channel stopper layer.

17. A method for producing a semiconductor device, the method comprising:

forming a drift region of a first conductivity type in a silicon-carbide (SiC) substrate of the first conductivity type;

forming a junction field-effect transistor (JFET) channel region of the first conductivity type in the SiC substrate above the drift region;

forming a shielding body region of a second conductivity type in the JFET channel region;

forming a channel stopper layer of the second conductivity type on the shielding body region;

forming a source region of the first conductivity type on the channel stopper layer;

forming a gate trench extending through the source region and the channel stopper layer, the gate trench terminating in the JFET channel region and having a sidewall and a bottom surface, the sidewall of the gate trench defining an angle of greater than 90 degrees with the bottom surface of the gate trench;

forming a built-in channel of the first conductivity type below the gate trench, the built-in channel having a sidewall portion disposed along at least a portion of the sidewall of the gate trench and a lateral portion disposed along at least a portion of the bottom surface of the gate trench, the lateral portion of the built-in channel having a threshold voltage that is less than a threshold voltage of the sidewall portion of the built-in channel;

forming a gate dielectric having a sidewall portion disposed on the sidewall of the gate trench and a lateral portion disposed on the bottom surface of the trench, the lateral portion of the gate dielectric having a thickness that is greater than or equal to two times a thickness of the sidewall portion of the gate dielectric; and

forming a gate electrode on the gate dielectric within the gate trench.

18. The method of claim 17, wherein forming the lateral portion of the gate dielectric includes forming a field oxide layer.

19. The method of claim 17, wherein the gate trench is a first trench, the method further comprising:

forming a second trench extending through the source region and the channel stopper layer, the second trench terminating in the shielding body region;

forming a sub-contact implant region of the second conductivity type in the shielding body region;

forming a linking implant of the first conductivity type, the linking implant extending from the sub-contact implant region to the source region, the linking implant having a lateral portion and a vertical portion; and

forming a contact layer on at least a portion of the sub-contact implant region and on at least a portion of the linking implant, the contact layer establishing a first ohmic contact with the sub-contact implant region and a second ohmic contact with the source region via the linking implant.

20. The method of claim 17, wherein the sidewall portion of the built-in channel is disposed below the channel stopper layer.