Method for forming a semiconductor device including a stacked wire structure

• US 10,355,133 B2
• Filed: 06/30/2017
• Issued: 07/16/2019
• Est. Priority Date: 11/20/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Cheng-Hsien, Yeh, Chih-Chieh, Yeo, Yee-Chia
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US15/640,303
• Publication Number:
  US 20170301787A1
• Time in Patent Office: 746 Days
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a stacked wire structure over a substrate and forming a gate structure across middle portions of the stacked wire structure. A trench can be formed by removing the gate structure, in which a middle portion of the stacked wire structure is exposed. The method further includes removing a portion of the stacked wire structure to form a recess and forming a source/drain (S/D) structure at two opposite sides of the stacked wire structure, where the S/D structure is formed by an epitaxial process and includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

Claims

1. A method for forming a semiconductor device structure, comprising:

forming a stacked wire structure over a substrate, wherein the stacked wire structure comprises a first semiconductor wire and a second semiconductor wire over the first semiconductor wire, and the first and second semiconductor wires comprise different materials;

forming a gate structure across middle portions of the stacked wire structure;

forming a source/drain (S/D) structure at two opposite sides of the stacked wire structure, wherein the S/D structure is formed by an epitaxial process and comprises a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface; and

growing a first portion of the S/D structure over sidewalls of the first semiconductor wire and a second portion of the S/D structure over sidewalls of the second semiconductor wire, wherein a growth rate of the first portion is different from a growth rate of the second portion.

2. The method of claim 1, wherein the S/D structure is grown on a (111) plane in a horizontal direction and on a (110) plane in a vertical direction.

3. The method of claim 1, wherein the S/D structure is grown on a (110) plane in a horizontal direction and on a (111) plane in a vertical direction.

4. The method of claim 1, further comprising:

removing the gate structure to form a trench, wherein a middle portion of the stacked wire structure is exposed;

removing a portion of the stacked wire structure to form a recess; and

forming a conductive material in the trench and the recess.

5. The method of claim 1, wherein the first and second portions of the S/D structure have a periodical wave-like profile.

6. The method of claim 1, wherein the first and second portions of the S/D structure are grown along a <

112>

, a <

111>

, or a <

100>

direction.

7. The method of claim 1, further comprising forming an isolation structure over the substrate, wherein a bottom surface of the stacked wire structure is level with a top surface of the isolation structure.

8. The method of claim 7, further comprising forming a fin structure extending above the substrate and embedded in the isolation structure.

9. The method of claim 1, further comprising:

forming a silicide layer over the S/D structure; and

forming a contact structure over the silicide layer.

10. The method of claim 1, further comprising forming a channel region in the stacked wire structure, wherein the channel region is formed along a <

112>

, a <

111>

, or a <

100>

direction.

18. The method of claim 1, wherein the substrate comprises silicon, germanium, silicon carbide, gallium arsenide, indium phosphide, or a combination thereof.

11. A method for forming a semiconductor device structure, comprising:

providing a substrate having a (110) surface orientation or a (111) surface orientation;

forming a fin structure extending above the substrate;

forming a first semiconductor wire over the fin structure;

forming a second semiconductor wire over the first semiconductor wire, wherein the first and second semiconductor wires are formed using different materials;

forming a gate structure over the first and second semiconductor wires; and

epitaxially growing first and second portions of a source/drain (S/D) structure respectively on the first and second semiconductor wires, wherein a growth rate of the first portion of the S/D structure is different from a growth rate of the second portion of the S/D structure.

12. The method of claim 11, further comprising forming a buffer layer between the fin structure and the substrate, wherein a lattice constant of the buffer layer is between lattice constants of the fin structure and the substrate.

13. The method of claim 11, further comprising forming a spacer between the gate structure and the S/D structure.

19. The method of claim 11, wherein the first or the second semiconductor wire comprises silicon, germanium, silicon germanium, indium arsenide, indium gallium arsenide, indium antimonide, or a combination thereof.

14. A method for forming a semiconductor structure, comprising:

providing a substrate having a (110) surface orientation or a (111) surface orientation;

forming a fin structure extending above the substrate;

forming first and second semiconductor wires of a stacked wire structure, wherein the second semiconductor wire is formed over the first semiconductor wire; and

epitaxially growing top and sidewall portions of a source/drain (S/D) structure, wherein a rounded corner is formed between the respective surfaces of the top and sidewall portions, wherein the top and sidewall portions of the S/D structure have different epitaxial growth rates.

15. The method of claim 14, wherein the sidewall portion of the S/D structure has a periodical wave-like profile.

16. The method of claim 14, wherein the S/D structure is epitaxially grown along a <

112>

, a <

111>

, or a <

100>

direction.

17. The method of claim 14, wherein the epitaxially growing the S/D structure comprises epitaxially growing at least one of silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), germanium arsenide (GaAs), germanium antimonide (GaSb), indium aluminum phosphide (InAlP), or indium phosphide (InP).

20. The method of claim 14, wherein the first or the second semiconductor wire is along a direction of <

112>

, <

111>

, or <

100>

.