Clock data recovery circuit, apparatus including same and method for recovery clock and data

• US 10,355,700 B2
• Filed: 10/03/2018
• Issued: 07/16/2019
• Est. Priority Date: 11/20/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Jung-Pil, Ryu, Kyung-Ho, Yu, Jae-Suk, Lee, Jae-Youl, Lee, Dong-Myung, Lim, Hyun-Wook
• Primary Examiner(s): Houston, Adam D
• Application Number:
  US16/150,347
• Publication Number:
  US 20190158100A1
• Time in Patent Office: 286 Days
• Field of Search: 327147-149, 327156-158
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit

Abstract

A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.

Claims

1. A clock data recovery circuit that receives an input data signal including an embedded clock, the clock data recovery circuit comprising:

a clock recovery circuit configured to generate a recovery clock signal from the input data signal based on a first window signal and to generate a second window signal synchronized with the recovery clock signal from the first window signal;

a delayed locked loop circuit configured to detect a unit interval corresponding to one bit of the input data signal based on the recovery clock signal and to generate a third window signal by delaying the second window signal based on the unit interval; and

a window generating circuit configured to generate the first window signal based on the third window signal and the recovery clock signal, so that a phase of the recovery clock signal is identical to a phase of the third window signal.

2. The clock data recovery circuit of claim 1, wherein a phase of the first window signal leads the phase of the recovery clock signal by approximately half of the unit interval.

3. The clock data recovery circuit of claim 1, wherein the clock recovery circuit comprises:

an edge detector configured to generate an edge detect signal by detecting edges of the input data signal;

a clock generator configured to generate the recovery clock signal by extracting an edge, from among the detected edges, that overlap an active interval of the first window signal; and

a window delay circuit configured to generate the second window signal by delaying the first window signal by a phase difference between a phase of the edge detect signal and the phase of the recovery clock signal.

4. The clock data recovery circuit of claim 1, wherein the delayed locked loop circuit comprises:

a clock delay circuit configured to delay the recovery clock signal based on a control signal to thereby generate a plurality of delayed clock signals;

a delay controller configured to generate the control signal,

wherein the clock delay circuit is configured to generate a first delayed clock signal, from among the plurality of delayed clock signals, as having a phase identical to the phase of the recovery clock signal; and

a window delay circuit configured to generate the third window signal from the second window signal based on the control signal.

5. The clock data recovery circuit of claim 4, wherein the clock delay circuit comprises a series of delay units configured to receive the recovery clock signal, and

the window delay circuit comprises at least one delay unit identical to each of the delay units of the series of delay units.

6. The clock data recovery circuit of claim 4, wherein the window generating circuit comprises:

a pulse generator configured to generate a pulse signal based on at least one of the plurality of delayed clock signals;

a phase detector configured to detect a phase difference between the phase of the recovery clock signal and the phase of the third window signal; and

a window signal generator configured to generate the first window signal by delaying the pulse signal based on the detected phase difference.

7. The clock data recovery circuit of claim 4, wherein the clock recovery circuit comprises a data delay circuit configured to generate an internal data signal synchronized with the recovery clock signal from the input data signal, and

the plurality of delayed clock signals comprise a plurality of sample clock signals having phase differences with respect to each other equivalent to multiples of the unit interval, and

the clock data recovery circuit further comprising a data recovery circuit configured to generate an output data signal by sampling the internal data signal based on the plurality of sample clock signals.

8. A clock data recovery circuit that receives an input data signal including an embedded clock, the clock data recovery circuit comprising:

a clock recovery circuit configured to generate a recovery clock signal by extracting periodic edges from the input data signal based on a first window signal and to generate a second window signal synchronized with the recovery clock signal from the first window signal;

a delayed locked loop circuit configured to detect a unit interval corresponding to one bit of the input data signal based on the recovery clock signal and to generate a plurality of delayed clock signals by delaying the recovery clock signal; and

a window generating circuit configured to generate the first window signal based on the second window signal and a delayed clock signal from among the plurality of delayed clock signals, so that a phase of the second window signal is identical to a phase of the delayed clock signal.

9. The clock data recovery circuit of claim 8, wherein the phase of the delayed clock signal leads a phase of the recovery clock signal by approximately half of the unit interval.

10. The clock data recovery circuit of claim 8, wherein the clock recovery circuit comprises:

an edge detector configured to generate an edge detect signal by detecting edges of the input data signal;

a clock generator configured to generate the recovery clock signal by detecting an edge, from among the detected edges, that overlaps an active interval of the first window signal; and

a window delay circuit configured to generate the second window signal by delaying the first window signal by a phase difference between a phase of the edge detect signal and a phase of the recovery clock signal.

11. The clock data recovery circuit of claim 8, wherein the delayed locked loop circuit comprises:

a clock delay circuit configured to delay the recovery clock signal based on a control signal to thereby generate the plurality of delayed clock signals; and

a delay controller configured to generate the control signal,

wherein the clock delay circuit is configured to generate a first delayed clock signal, from among the plurality of delayed clock signals, as having a phase identical to a phase of the recovery clock signal.

12. The clock data recovery circuit of claim 11, wherein the window generating circuit comprises:

a pulse generator configured to generate a pulse signal based on at least one of the plurality of delayed clock signals;

a phase detector configured to detect a phase difference between the phase of the second window signal and the phase of the delayed clock signal; and

a window signal generator configured to generate the first window signal by delaying the pulse signal based on the detected phase difference.

13. A method of recovering a clock and data from an input data signal including an embedded clock, the method comprising:

generating a recovery clock signal from the input data signal based on a first window signal;

detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal;

delaying a signal synchronized with the recovery clock signal based on the unit interval to provide a delayed signal; and

generating the first window signal based on the delayed signal.

14. The method of claim 13, further comprising:

generating a second window signal synchronized with the recovery clock signal from the first window signal,

wherein the delaying the signal synchronized with the recovery clock signal comprises generating a third window signal as the delayed signal by delaying the second window signal based on the unit interval, and

the generating the first window signal comprises generating the first window signal based on the recovery clock signal and the third window signal.

15. The method of claim 14, wherein the generating the first window signal comprises:

detecting a phase difference between a phase of the recovery clock signal and a phase of the third window signal; and

generating the first window signal so that the phase difference is zero.

16. The method of claim 14, wherein the generating the third window signal comprises generating the third window signal by delaying the second window signal by approximately half of the unit interval.

17. The method of claim 13, further comprising generating a second window signal synchronized with the recovery clock signal from the first window signal,

wherein the delaying the signal synchronized with the recovery clock signal comprises generating a delayed clock signal as the delayed signal by delaying the recovery clock signal based on the unit interval, and

the generating the first window signal comprises generating the first window signal based on the second window signal and the delayed clock signal.

18. The method of claim 17, wherein the generating the first window signal comprises:

detecting a phase difference between a phase of the second window signal and a phase of the second delayed clock signal; and

generating the first window signal so that the phase difference is zero.

19. The method of claim 17, wherein the generating the delayed clock signal comprises generating the delayed clock signal that precedes the recovery clock signal by approximately half of the unit interval.

20. The method of claim 13, wherein the detecting the unit interval comprises:

generating a plurality of delayed clock signals by passing the recovery clock signal through a series of delay units; and

controlling the series of delay units so that a phase of a first delayed clock signal from among the plurality of delayed clock signals is identical to a phase of the recovery clock signal.