Use of multiple codebooks for programming data in different memory areas of a storage device

• US 10,355,712 B2
• Filed: 03/31/2017
• Issued: 07/16/2019
• Est. Priority Date: 03/31/2017
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Rom, Rami, Goldenberg, Idan, Bazarsky, Alexander, Sharon, Eran, Zamir, Ran, Alrod, Idan, Achtenberg, Stella
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/475,602
• Publication Number:
  US 20180287634A1
• Time in Patent Office: 837 Days
• Field of Search: 714763, 714718, 714768, 714770, 714773, 714786, 714799, 714 622, 714 624, 714 25, 365200, 365201, 36518509
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1125 using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/118 Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure H03M13/1165 takes precedence
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Claims

1. A storage device comprising:

a memory comprising a plurality of different memory areas, including a first memory area and a second memory area;

a controller configured to;

encode a first data set with a first codebook to generate a first codeword, the first codebook associated with the first memory area;

encode a second data set with a second codebook to generate a second codeword, the second codebook associated with the second memory area; and

program the first codeword into the first memory area and the second codeword into the second memory area, wherein the first codebook and the second codebook are permutations of a common codebook and at least one of the first codebook or the second codebook has a reduced number of bad or weak variable nodes connected to a check node compared to a number of bad variable nodes connected to the check node of the common codebook.

2. The storage device of claim 1, wherein the controller is further configured to:

prior to encoding the first data set, access a codebook database storing a plurality of codebooks to identify an association between the first codebook and the first memory area, and select the first codebook among the plurality of codebooks based on identification of the association.

3. The storage device of claim 2, wherein the codebook database associates the plurality of different memory areas with the plurality of codebooks on a per-die basis, a per-plane basis, a per-block basis, a per-page basis, or a per-segment basis.

4. The storage device of claim 2, wherein the first codebook provides optimum decoding performance for the first memory area compared to the other codebooks in the codebook database, and the second codebook provides optimum decoding performance for the second memory area compared to the other codebooks in the codebook database.

5. The storage device of claim 1, wherein an associated parity-check matrix of the common codebook has at least one minimal cycle that is removed in the first codebook.

6. The storage device of claim 1, wherein the first codebook has an associated parity-check matrix comprising at least two columns that are swapped compared to an associated parity-check matrix of the common codebook.

7. The storage device of claim 1, wherein the first codebook comprises a first sub-codebook, and the second codebook comprises a second sub-codebook, and wherein the first sub-codebook and the second sub-codebook are configured to generate different numbers of sub-code parity bits for the first data set and the second data set, respectively.

8. The storage device of claim 1, wherein the first memory area and the second memory area comprise different sets of bad or weak storage locations.

9. The storage device of claim 1, wherein the plurality of different memory areas comprises different dies, different planes, different blocks, different pages, or different segments of the memory.

10. A storage device comprising:

a memory comprising a plurality of different memory areas, including a first memory area and a second memory area;

a controller configured to;

encode a first data set with a first codebook to generate a first codeword, the first codebook associated with the first memory area;

encode a second data set with a second codebook to generate a second codeword, the second codebook associated with the second memory area; and

program the first codeword into the first memory area and the second codeword into the second memory area, wherein the first codebook and the second codebook are permutations of a common codebook and an associated parity-check matrix of the common codebook has at least one minimal cycle that is removed in the first codebook.

11. The storage device of claim 10, wherein the controller is further configured to:

receive a program request to program the second data set into the memory;

identify the second memory area of the plurality of different memory areas into which to program the second data set;

select the second codebook among the plurality of different codebooks based on the association between the second memory area and the second codebook.

12. The storage device of claim 10, wherein the plurality of different memory areas comprises different dies, different planes, different blocks, different pages, or different segments of the memory.

13. A storage device comprising:

a memory comprising a plurality of different memory areas, including a first memory area and a second memory area;

a controller configured to;

encode a first data set with a first codebook to generate a first codeword, the first codebook associated with the first memory area;

encode a second data set with a second codebook to generate a second codeword, the second codebook associated with the second memory area; and

program the first codeword into the first memory area and the second codeword into the second memory area, wherein the first codebook and the second codebook are permutations of a common codebook and the first codebook has an associated parity-check matrix comprising at least two columns that are swapped compared to an associated parity-check matrix of the common codebook.

14. A storage device comprising:

a memory comprising a plurality of different memory areas, including a first memory area and a second memory area;

a controller configured to;

encode a first data set with a first codebook to generate a first codeword, the first codebook associated with the first memory area;

encode a second data set with a second codebook to generate a second codeword, the second codebook associated with the second memory area; and

program the first codeword into the first memory area and the second codeword into the second memory area, wherein the first codebook and the second codebook are permutations of a common codebook and the first codebook comprises a first sub-codebook, and the second codebook comprises a second sub-codebook, and wherein the first sub-codebook and the second sub-codebook are configured to generate different numbers of sub-code parity bits for the first data set and the second data set, respectively.

15. The storage device of claim 14, wherein the controller is further configured to:

prior to encoding the first data set, access a codebook database storing a plurality of codebooks to identify an association between the first codebook and the first memory area; and

select the first codebook among the plurality of codebooks based on identification of the association.

16. The storage device of claim 15, wherein the first codebook provides optimum decoding performance for the first memory area compared to the other codebooks in the codebook database, and the second codebook provides optimum decoding performance for the second memory area compared to the other codebooks in the codebook database.

17. The storage device of claim 16, wherein the codebook database associates the plurality of different memory areas with the plurality of codebooks on a per-die basis, a per-plane basis, a per-block basis, a per-page basis, or a per-segment basis.

18. The storage device of claim 14, wherein at least one of the first codebook or the second codebook has a reduced number of bad or weak variable nodes connected to a check node compared to a number of bad variable nodes connected to the check node of the common codebook.