Lock detector for phase lock loop

• US 10,355,852 B2
• Filed: 02/26/2018
• Issued: 07/16/2019
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Tayong, Helene E
• Application Number:
  US15/905,614
• Publication Number:
  US 20180183566A1
• Time in Patent Office: 505 Days
• Field of Search: 375355
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.

Claims

1. A method comprising:

obtaining a plurality of phases of a local clock signal from a voltage-controlled oscillator (VCO) comprising a plurality of sequentially-connected logic elements, each phase obtained via an output of a respective logic element;

generating a frequency-lock assist (FLA) signal by detecting transitions in each phase of the plurality of phases of the local clock signal in adjacent sampling instants determined by a reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the local clock signal and the reference clock signal; and

applying the FLA signal to an error accumulation circuit, the error accumulation circuit generating a VCO control signal for setting the VCO in a frequency-locked condition based at least on the FLA signal.

2. The method of claim 1, wherein the FLA signal is applied to a first-order input of the error accumulation circuit.

3. The method of claim 2, wherein the first-order input is a capacitive input of an RC filter in the error accumulation circuit.

4. The method of claim 1, wherein setting the VCO in the frequency-locked condition comprises adjusting gate propagation delay of the plurality of sequentially-connected logic elements.

5. The method of claim 1, wherein setting the VCO in the frequency-locked condition comprises adjusting inter-gate rise and fall time of the plurality of sequentially-connected logic elements.

6. The method of claim 1, further comprising setting the VCO in a phase-locked condition based on a phase error signal generated by a phase comparator operating on a phase of the plurality of phases of the local clock signal and the reference clock signal.

7. The method of claim 6, further comprising providing the phase-error signal to a second-order input of the error accumulation circuit.

8. The method of claim 1, wherein generating the FLA signal comprises generating a plurality of partial FLA signals, and forming a summation of the plurality of partial FLA signals to generate the FLA signal.

9. The method of claim 8, wherein each partial FLA signal is formed by a respective FLA sub-circuit operating on (i) the reference signal and (ii) a respective phase of the plurality of phases of the local clock signal.

10. The method of claim 1, further comprising low-pass filtering the VCO control signal.

11. An apparatus comprising:

a voltage-controlled oscillator (VCO) comprising a plurality of sequentially-connected logic elements, the VCO configured to provide a plurality of phases of a local clock signal, each phase provided via an output of a respective logic element of the plurality of sequentially-connected logic elements;

a frequency-lock assist (FLA) circuit configured to generate an FLA signal by detecting transitions in each phase of the plurality of phases of the local clock signal in adjacent sampling instants determined by a reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the local clock signal and the reference clock signal; and

an error accumulation circuit configured to receive the FLA, the error accumulation circuit configured to generate a VCO control signal to set the VCO in a frequency-locked condition based at least on the received FLA signal.

12. The apparatus of claim 11, wherein the error accumulation circuit is configured to receive the FLA signal at a first-order input.

13. The apparatus of claim 12, wherein the first-order input is a capacitive input of an RC filter in the error accumulation circuit.

14. The apparatus of claim 11, wherein the VCO control signal is configured to adjust gate propagation delay of the plurality of sequentially-connected logic elements to set the VCO in the frequency-locked condition.

15. The apparatus of claim 11, wherein the VCO control signal is configured to adjust inter-gate rise and fall time of the plurality of sequentially-connected logic elements to set the VCO in the frequency-locked condition.

16. The apparatus of claim 11, further comprising a phase comparator configured to receive a phase of the plurality of phases of the local clock signal and the reference signal and to responsively generate a phase-error signal representing a phase-offset between the phase of the plurality of phases of the local clock signal and the reference signal, the phase-error signal provided to the error accumulation circuit.

17. The apparatus of claim 16, wherein the error accumulation circuit comprises a second-order input configured to receive the phase-error signal.

18. The apparatus of claim 11, wherein the FLA circuit comprises a plurality of FLA sub-circuits, the plurality of FLA sub-circuits configured to generate a plurality of partial FLA signals, and wherein the FLA circuit is configured to form a summation of the plurality of partial FLA signals to generate the FLA signal.

19. The apparatus of claim 18, wherein each partial FLA signal is formed by a respective FLA sub-circuit operating on (i) the reference signal and (ii) a respective phase of the plurality of phases of the local clock signal.

20. The apparatus of claim 11, further comprising a low-pass filter configured to low-pass filter the VCO control signal.