Multiplexing distinct signals on a single pin of a memory device

• US 10,355,893 B2
• Filed: 05/11/2018
• Issued: 07/16/2019
• Est. Priority Date: 10/02/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hasbun, Robert Nasry, Hollis, Timothy M., Wright, Jeffrey P., Gans, Dean D.
• Primary Examiner(s): Nguyen, Vanthu T
• Application Number:
  US15/977,813
• Publication Number:
  US 20190103148A1
• Time in Patent Office: 431 Days
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G11C 2207/101 Analog or multilevel bus
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

Claims

1. An apparatus, comprising:

a first memory die coupled with a bus;

a second memory die coupled with the bus;

a third memory die coupled with the bus; and

a memory controller coupled with the bus, wherein the memory controller is operable to;

identify first data, second data, and third data;

multiplex the first data, the second data, and the third data in a signal modulated using a first modulation scheme having at least five levels; and

transmit the signal to the first memory die, the second memory die, and the third memory die.

2. The apparatus of claim 1, wherein at least one of the first data, the second data, or the third data comprise metadata, control data, or storage data.

3. The apparatus of claim 1, wherein the first memory die, the second memory die, and the third memory die each comprise at least one of ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), a NAND device, a NOR device, or a phase-change memory device.