Ethernet relay

• US 10,355,990 B2
• Filed: 03/10/2015
• Issued: 07/16/2019
• Est. Priority Date: 03/10/2014
• Status: Active Grant

• Current Assignee: Sckipio Technologies S.I Ltd.
• Original Assignee: Sckipio Technologies S.I Ltd.
• Inventors: Sterenson, Ron, Reina, Guy
• Primary Examiner(s): Duong, Duc T
• Application Number:
  US15/124,581
• Publication Number:
  US 20170111270A1
• Time in Patent Office: 1,589 Days
• Field of Search: None
• CPC Class Codes: H04B 10/272 Star-type networks or tree-type networks
• CPC Class Codes: H04L 12/00 Data switching networks interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: H04L 12/2869 Operational details of access network equipments admission control or resource allocation in access networks H04L12/5692
• CPC Class Codes: H04L 12/2892 characterised by the access multiplexer architecture
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 45/16 Multipoint routing
• CPC Class Codes: H04L 45/66 Layer 2 routing, e.g. in Ethernet based MAN's
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/35 Switches specially adapted for specific applications

Abstract

A multi-port access node, for communicating data to-and-fro a plurality of transceiver units via a plurality of respective communication lines, comprising: a plurality of processors, each processor includes a main communication unit that includes a network-side port, said processor includes at least one line-side port associated with a respective one of said communication lines, at least one of said processors further includes a relay unit having a relay port, said relay unit Is coupled with said main communication unit of the same said processor, said relay port is coupled with at least one of said network-side port of at least one different said processor, wherein said relay unit is configured to relay at least part of said data in at least one of a downstream direction destined toward at least one of said transceiver units, and an upstream direction arriving from at least one of said transceiver units.

Claims

1. A multi port access node for communicating data to and fro a plurality of transceiver units via a plurality of respective communication lines, the multi port access node comprising:

a plurality of processors forming a cascade configuration defining a first processor, each processor includes a main communication unit, said main communication unit includes a network side port, said processor includes at least one line side port associated with a respective one of said communication lines, at least one of said processors further includes a relay unit having a relay port, said relay unit is coupled with said main communication unit of the same said processor, said relay port is coupled with at least one said network side port of at least one different said processor, wherein said first processor is configured to aggregate a flow control state associated with each of said processors in said cascade configuration, and to generate its respective local PAUSE data, wherein said relay unit is configured to relay at least part of said data in at least one of a downstream direction destined toward at least one of said transceiver units, and an upstream direction arriving from at least one of said transceiver units.

2. The multi port access node according to claim 1, wherein said relay unit is configured to relay said data to said main communication unit located within the same said processor.

3. The multi port access node according to claim 1, wherein said relay unit is configured to relay said data to said main communication unit of said at least one different said processor.

4. The multi-port access node according to claim 1, wherein said network side port, of at least one of said processors that includes said relay unit, is configured for coupling with and external host.

5. The multi port access node according to claim 4, wherein successive coupling between said processors forms at least one cascaded relay configuration, where said first processor is configured to be coupled with said external host is within its respective said at least one cascaded relay configuration.

6. The multi port access node according to claim 5, wherein a last said processor in said cascaded relay configuration drops said data that is not destined to any of said at least one line side ports.

7. The multi port access node according to claim 5, wherein in said upstream direction, said data said arriving from said transceiver units are aggregated by each said processor in said cascaded relay configuration.

8. The multi port access node according to claim 5, wherein each said processor is configured to generate its own respective local PAUSE data that is relayed through said cascade configuration.

9. The multi port access node according to claim 8, wherein said flow control state is communicated along said at least one cascaded relay configuration, through a respective local PAUSE frame message.

10. The multi port access node according to claim 9, wherein said first processor is configured to generate a global PAUSE message from every said respective local PAUSE frame message.

11. The multi port access node according to claim 10, wherein said first processor further combines its corresponding said flow control state with said flow control state corresponding to the remaining said processors into an aggregated flow control state.

12. The multi port access node according to claim 11, wherein said first processor is configured to output a standardized PAUSE message that contains aggregated data pertaining to individual said flow control state associated with each of said processors.

13. The multi port access node according to claim 9, wherein said local PAUSE frame contains at least one of the following information:

said flow control state of local data streams in said processor, that is represented by a bit map;

a number of active said local data streams in said bit map of said processor; and

bit positions within an aggregate flow control register indicating where a local flow control bit map is located.

14. The multi port access node according to claim 1, wherein said processors exchange with each other precoding data used for vectoring, via a vectoring bus.

15. The multi port access node according to claim 1, wherein said processor relays at least part of said data that is not destined toward its own said at least one line side port, toward said at least one different said processor.

16. The multi port access node according to claim 1, wherein in said downstream direction, different parts of said data are relayed to different respective said transceiver units.

17. The multi port access node according to claim 1, wherein said main communication unit of said processor conveys a back pressure signal toward said relay unit of said at least one different said processor, wherein said back-pressure signal carries information pertaining to the capability of said main communication unit to receive further said data.

18. The multi port access node according to claim 1, wherein said main communication unit inspects said data received on its respective said network side port, and filters said data not destined to its respective said at least one line side port.

19. The multi port access node according to claim 1, wherein said main communication unit includes a main media access controller (MAC) and a main physical coding sub layer (PCS) block that are coupled with each other.

20. The multi port access node according to claim 19, wherein said relay unit includes a relay MAC, a relay PCS block, a serializer/deserializer (SERDES), and a multiplexer, said relay MAC is coupled with said relay PCS block, said relay PCS block is coupled with said multiplexer, and said SERDES is coupled with said multiplexer, said main PCS block and with said relay PCS block.

21. The multi port access node according to claim 20, wherein said SERDES of said processor is coupled with said SERDES of said at least one different said processor.

22. The multi port access node according to claim 21, wherein in said downstream direction, said at least part of said data traverses at least part of a downstream path defined from an external host, via said SERDES, via said main PCS block, via said main MAC, via said relay PCS block, via said multiplexer, and via said SERDES again.

23. The multi port access node according to claim 21, wherein in said upstream direction, said at least part of said data traverses at least part of an upstream path defined from said at least one of said transceiver units, toward said SERDES, via said relay PCS block, via said relay MAC, via said main MAC, via said main PCS block, via said SERDES again.

24. The multi port access node according to claim 21, wherein management data is communicated from said processor to said at least one different processor.