Systems and methods to visually align signals using delay

• US 10,356,001 B1
• Filed: 02/08/2019
• Issued: 07/16/2019
• Est. Priority Date: 05/09/2018
• Status: Active Grant

• Current Assignee: BioSig Technologies, Inc.
• Original Assignee: BioSig Technologies, Inc.
• Inventors: Drakulic, Budimir S., Fakhar, Sina, Foxall, Thomas G., Vlajinic, Branislav
• Primary Examiner(s): Boutah, Alina A
• Application Number:
  US16/271,462
• Time in Patent Office: 158 Days
• CPC Class Codes: A61B 18/1492 having a flexible, catheter-like structure, e.g. for heart ablation A61B18/1477 takes precedence
• CPC Class Codes: A61B 2018/00351 Heart
• CPC Class Codes: A61B 2018/00577 Ablation
• CPC Class Codes: A61B 2562/18 Shielding or protection of sensors from environmental influences, e.g. protection from mechanical damage
• CPC Class Codes: A61B 2562/223 Optical cables therefor
• CPC Class Codes: A61B 5/0006 ECG or EEG signals
• CPC Class Codes: A61B 5/0215 by means inserted into the body catheters A61M25/00
• CPC Class Codes: A61B 5/02405 Determining heart rate variability
• CPC Class Codes: A61B 5/0245 by using sensing means generating electric signals, i.e. ECG signals
• CPC Class Codes: A61B 5/0538 invasively, e.g. using a catheter
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/308 for electrocardiography [ECG]
• CPC Class Codes: A61B 5/316 Modalities, i.e. specific diagnostic methods
• CPC Class Codes: A61B 5/318 Heart-related electrical modalities, e.g. electrocardiography [ECG]
• CPC Class Codes: A61B 5/352 Detecting R peaks, e.g. for synchronising diagnostic apparatus; Estimating R-R interval
• CPC Class Codes: A61B 5/361 Detecting fibrillation
• CPC Class Codes: A61B 5/363 Detecting tachycardia or bradycardia
• CPC Class Codes: A61B 5/366 Detecting abnormal QRS complex, e.g. widening
• CPC Class Codes: A61B 5/4836 Diagnosis combined with treatment in closed-loop systems or methods A61B5/0036 takes precedence
• CPC Class Codes: A61B 5/7203 for noise prevention, reduction or removal
• CPC Class Codes: A61B 5/7217 : of noise originating from a therapeutic or surgical apparatus, e.g. from a pacemaker
• CPC Class Codes: A61B 5/7221 : Determining signal validity, reliability or quality A61B5/7207 and A61B5/7217 take precedence
• CPC Class Codes: A61B 5/7225 : Details of analog processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation A61B5/30, A61B5/316 take precedence; transformers for specific applications H01F38/00; amplifiers H03F
• CPC Class Codes: A61B 5/7246 : using correlation, e.g. template matching or determination of similarity
• CPC Class Codes: A61B 5/742 : using visual displays A61B5/339 takes precedence
• CPC Class Codes: A61B 5/7435 : Displaying user selection data, e.g. icons in a graphical user interface
• CPC Class Codes: G16H 40/63 : for local operation
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H02H 9/04 : responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T
• CPC Class Codes: H02H 9/045 : adapted to a particular application and not provided for elsewhere
• CPC Class Codes: H03F 2200/129 : there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/171 : A filter circuit coupled to the output of an amplifier
• CPC Class Codes: H03F 2200/234 : the input amplifying stage being one or more operational amplifiers
• CPC Class Codes: H03F 2200/375 : Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45116 : Feedback coupled to the input of the differential amplifier
• CPC Class Codes: H03F 2203/45528 : the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45601 : the IC comprising one or more passive resistors by feedback
• CPC Class Codes: H03F 3/45 : Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45475 : using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03H 2017/0298 : DSP implementation
• CPC Class Codes: H03K 5/125 : Discriminating pulses measuring characteristics of individual pulses G01R29/02; separation of synchronising signals in television systems H04N5/08
• CPC Class Codes: H04B 1/0014 : using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04B 1/0039 : using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04L 43/02 : Capturing of monitoring data
• CPC Class Codes: H04L 47/50 : Queue scheduling

Abstract

Systems, methods, and computer program product embodiments are disclosed for processing and displaying multiple signals in near real-time. An embodiment operates by processing, using a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal. The embodiment also processes, using a second DSP of a second signal module, a second packet associated with a second signal. The embodiment equalizes a first processing delay associated with the first DSP with a second processing delay associated with the second DSP such that the first DSP completes processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet. The embodiment then displays the processed first packet approximately simultaneously with the display of the processed second packet.

Claims

1. A system for visualization of signals, comprising:

a memory comprising;

an input module configured to receive and store signal samples of a first signal;

a packetizer module configured to;

select, and store into a first packet, a portion of the signal samples of the first signal for a first time period, wherein the first packet comprises a first tag corresponding to the first time period; and

select, and store into a second packet, a portion of signal samples of a second signal for the first time period, wherein the second packet comprises a second tag corresponding to the first time period;

a first signal module comprising a first digital signal processor (DSP) configured to process the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;

a second signal module comprising a second DSP configured to process the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;

a configuration path module configured to equalize the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

a display module coupled to the first signal module and the second signal module and configured to display the processed first packet and the processed second packet, wherein the display module is configured to display the processed first packet approximately simultaneously with the processed second packet; and

at least one processor coupled to the memory and configured to execute the input module, the packetizer module, the first signal module, the second signal module, the configuration path module, and the display module.

2. The system of claim 1, wherein the memory further comprises a queuing module configured to:

store the first packet in a first queue associated with the first signal, wherein the first queue enables the first packet to be processed independently; and

store the second packet in a second queue associated with the second signal, wherein the second queue enables the second packet to be processed independently; and

wherein the memory further comprises a packet dispatcher module configured to;

dispatch the first packet from the first queue to the first signal module based on a global signals table; and

dispatch the second packet from the second queue to the second signal module based on the global signals table.

3. The system of claim 1,

wherein the first DSP is further configured to process the first packet based on the first tag that corresponds to the first time period;

and

wherein the second DSP is further configured to process the second packet based on the second tag that corresponds to the first time period, wherein signal samples in the first packet are time aligned with signal samples in the second packet.

4. The system of claim 1, wherein the configuration path module is further configured to:

create the first signal module based on a first signal processing specification, and the second signal module based on a second signal processing specification, wherein the first signal module comprises a first input packet queue and a first output packet queue, and the second signal module comprises a second input packet queue and a second output packet queue; and

add the first signal module and the second signal module to a global signals table,

wherein the adding enables the first signal module to be dynamically assigned to a first set of signals and the second signal module to be dynamically assigned to a second set of signals, and

wherein a first assignment of the first signal module to the first set of signals enables the first signal module to process the first set of signals based on the first signal processing specification, and a second assignment of the second signal module to the second set of signals enables the second signal module to process the second set of signals based on the second signal processing specification.

5. The system of claim 4, wherein the first DSP is further configured to:

process the first packet using a first digital signal processing function associated with the first signal processing specification; and

output the processed first packet to the first output packet queue;

wherein the second DSP is further configured to;

process the second packet using a second digital signal processing function associated with the second signal processing specification; and

output the processed second packet to the second output packet queue, wherein the second DSP is configured to output the processed second packet to the second output packet queue approximately simultaneously with the first DSP outputting the processed first packet to the first output packet queue.

6. The system of claim 5, wherein signal samples in the processed first packet in the first output packet queue are time aligned with signal samples in the second packet in the second output packet queue.

7. The system of claim 5, wherein the display module is further configured to:

receive the processed first packet from the first output packet queue of the first signal module based on the first tag that corresponds to the first time period;

receive the processed second packet from the second output packet queue of the second signal module based on the second tag that corresponds to the first time period; and

display the processed first packet and the processed second packet simultaneously and in a non-overlapping format.

8. The system of claim 1, wherein the memory further comprises a monitoring path module comprising a queue monitor module and a reporting module,

wherein the queue monitor module is configured to determine, at a periodic interval, a first error status of the first input packet queue of the first signal module or a second error status of the second input packet queue of the second signal module, wherein the first error status or the second error status indicates a queue length violation, and

wherein the reporting module is configured to display the first error status of the first input packet queue of the first signal module or the second error status of the second input packet queue of the second signal module, wherein the display of the first error status or the second error status enables a user to reset the input module, the global signals table, the configuration path module, or an output module.

9. A computer implemented method for visualizing signals, comprising:

receiving and storing, by at least one processor executing an input module, signal samples of a first signal;

selecting, and storing into a first packet, by the at least one processor executing a packetizer module, a portion of the signal samples of the first signal for a first time period, wherein the first packet comprises a first tag corresponding to the first time period;

selecting, and storing into a second packet, by the at least one processor executing the packetizer module, a portion of signal samples of the second signal for the first time period, wherein the second packet comprises a second tag corresponding to the first time period;

processing, by the at least one processor executing a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;

processing, by the at least one processor executing a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;

equalizing, by the at least one processor executing a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP,

wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet being displayed.

10. The method of claim 9, further comprising:

storing, by the at least one processor executing a queueing module, the first packet in a first queue associated with the first signal, wherein the first queue enables the first packet to be processed independently;

storing, by the at least one processor executing the queueing module, the second packet in a second queue associated with the second signal, wherein the second queue enables the second packet to be processed independently;

dispatching, by the at least one processor executing a packet dispatcher module, the first packet from the first queue to the first signal module based on a global signals table; and

dispatching, by the at least one processor executing the packet dispatcher module, the second packet from the second queue to the second signal module based on the global signals table.

11. The method of claim 9, further comprising:

processing, by the at least one processor executing the first DSP, the first packet based on the first tag that corresponds to the first time period; and

processing, by the at least one processor executing the second DSP, the second packet based on the second tag that corresponds to the first time period, wherein signal samples in the first packet are time aligned with signal samples in the second packet.

12. The method of claim 9, further comprising:

creating, by the at least one processor executing the configuration path module, the first signal module based on a first signal processing specification, and the second signal module based on a second signal processing specification, wherein the first signal module comprises a first input packet queue and a first output packet queue, and the second signal module comprises a second input packet queue and a second output packet queue; and

adding, by the at least one processor executing the configuration path module, the first signal module and the second signal module to a global signals table,

wherein the adding enables the first signal module to be dynamically assigned to a first set of signals and the second signal module to be dynamically assigned to a second set of signals, and

wherein a first assignment of the first signal module to the first set of signals enables the first signal module to process the first set of signals based on the first signal processing specification, and a second assignment of the second signal module to the second set of signals enables the second signal module to process the second set of signals based on the second signal processing specification.

13. The method of claim 12, further comprising:

processing, by the at least one processor executing the first DSP, the first packet using a first digital signal processing function associated with the first signal processing specification;

outputting, by the at least one processor executing the first DSP, the processed first packet to the first output packet queue;

processing, by the at least one processor executing the second DSP, the second packet using a second digital signal processing function associated with the second signal processing specification; and

outputting, by the at least one processor executing the second DSP, the processed second packet to the second output packet queue, wherein the second DSP is configured to output the processed second packet to the second output packet queue approximately simultaneously with the first DSP outputting the processed first packet to the first output packet queue.

14. The method of claim 13, wherein signal samples in the processed first packet in the first output packet queue are time aligned with signal samples in the second packet in the second output packet queue.

15. The method of claim 13, further comprising:

receiving, by the at least one processor executing the display module, the processed first packet from the first output packet queue of the first signal module based on the first tag that corresponds to the first time period;

receiving, by the at least one processor executing the display module, the processed second packet from the second output packet queue of the second signal module based on the second tag that corresponds to the first time period; and

displaying, by the at least one processor executing the display module, the processed first packet and the processed second packet simultaneously and in a non-overlapping format.

16. The method of claim 12, further comprising:

determining, by the at least one processor executing a queue monitor module, at a periodic interval, a first error status of the first input packet queue of the first signal module or a second error status of the second input packet queue of the second signal module, wherein the first error status or the second error status indicates a queue length violation; and

displaying, by the at least one processor executing a reporting module, the first error status of the first input packet queue of the first signal module or the second error status of the second input packet queue of the second signal module, wherein the display of the first error status or the second error status enables a user to reset the input module, the global signals table, the configuration path module, or an output module.

17. A non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

receiving and storing, by an input module, signal samples of a first signal;

selecting, and storing into a first packet, by a packetizer module, the signal samples of the first signal for a first time period, wherein the first packet comprises a first tag corresponding to the first time period;

selecting, and storing into a second packet, by the packetizer module, a portion of signal samples of a second signal for the first time period, wherein the second packet comprises a second tag corresponding to the first time period;

processing, by a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;

processing, by a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;

equalizing, by a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

displaying, by a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet being displayed.

18. The non-transitory computer-readable device of claim 17, the operations further comprising:

storing, by a queueing module, the first packet in a first queue associated with the first signal, wherein the first queue enables the first packet to be processed independently;

storing, by the queueing module, the second packet in a second queue associated with the second signal, wherein the second queue enables the second packet to be processed independently;

dispatching, by a packet dispatcher module, the first packet from the first queue to the first signal module based on a global signals table; and

dispatching, by the packet dispatcher module, the second packet from the second queue to the second signal module based on the global signals table.

19. The non-transitory computer-readable device of claim 17, the operations further comprising:

processing, by the first DSP, the first packet based on a first tag that corresponds to the first time period; and

processing, by the second DSP, the second packet based on the second tag that corresponds to the first time period, wherein signal samples in the first packet are time aligned with signal samples in the second packet.

20. The non-transitory computer-readable device of claim 17, the operations further comprising:

creating, by the configuration path module, the first signal module based on a first signal processing specification, and the second signal module based on a second signal processing specification, wherein the first signal module comprises a first input packet queue and a first output packet queue, and the second signal module comprises a second input packet queue and a second output packet queue; and

adding, by the configuration path module, the first signal module and the second signal module to a global signals table,

wherein the adding enables the first signal module to be dynamically assigned to a first set of signals and the second signal module to be dynamically assigned to a second set of signals, and

wherein a first assignment of the first signal module to the first set of signals enables the first signal module to process the first set of signals based on the first signal processing specification, and a second assignment of the second signal module to the second set of signals enables the second signal module to process the second set of signals based on the second signal processing specification.

21. The non-transitory computer-readable device of claim 20, the operations further comprising:

processing, by the first DSP, the first packet using a first digital signal processing function associated with the first signal processing specification;

outputting, by the first DSP, the processed first packet to the first output packet queue;

processing, by the second DSP, the second packet using a second digital signal processing function associated with the second signal processing specification; and

outputting, by the second DSP, the processed second packet to the second output packet queue, wherein the second DSP is configured to output the processed second packet to the second output packet queue approximately simultaneously with the first DSP outputting the processed first packet to the first output packet queue.

22. The non-transitory computer-readable device of claim 21, wherein signal samples in the processed first packet in the first output packet queue are time aligned with signal samples in the second packet in the second output packet queue.

23. The non-transitory computer-readable device of claim 21, the operations further comprising:

receiving, by the display module, the processed first packet from the first output packet queue of the first signal module based on the first tag that corresponds to the first time period;

receiving, by the display module, the processed second packet from the second output packet queue of the second signal module based on the second tag that corresponds to the first time period; and

displaying, by the display module, the processed first packet and the processed second packet simultaneously and in a non-overlapping format.

24. The non-transitory computer-readable device of claim 20, the operations further comprising:

determining, by a queue monitor module, at a periodic interval, a first error status of the first input packet queue of the first signal module or a second error status of the second input packet queue of the second signal module, wherein the first error status or the second error status indicates a queue length violation; and

displaying, by a reporting module, the first error status of the first input packet queue of the first signal module or the second error status of the second input packet queue of the second signal module, wherein the display of the first error status or the second error status enables a user to reset the input module, the global signals table, the configuration path module, or an output module.

25. A system for visualization of signals, comprising:

a memory comprising;

a queuing module configured to;

store a first packet in a first queue associated with a first signal, wherein the first queue enables the first packet to be processed independently; and

store a second packet in a second queue associated with a second signal, wherein the second queue enables the second packet to be processed independently;

a first signal module comprising a first digital signal processor (DSP) configured to process the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;

a second signal module comprising a second DSP configured to process the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;

a packet dispatcher module configured to;

dispatch the first packet from the first queue to the first signal module based on a global signals table; and

dispatch the second packet from the second queue to the second signal module based on the global signals table;

a configuration path module configured to equalize the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

a display module coupled to the first signal module and the second signal module and configured to display the processed first packet and the processed second packet, wherein the display module is configured to display the processed first packet approximately simultaneously with the processed second packet; and

at least one processor coupled to the memory and configured to execute the queuing module, the first signal module, the second signal module, the packet dispatcher module, the configuration path module, and the display module.

26. A system for visualization of signals, comprising:

a memory comprising;

a first signal module comprising a first digital signal processor (DSP) configured to process a first packet associated with a first signal based on a first tag that corresponds to a first time period, wherein the processing of the first packet incurs a first processing delay;

a second signal module comprising a second DSP configured to process a second packet associated with a second signal based on a second tag that corresponds to the first time period, wherein the processing of the second packet incurs a second processing delay, and wherein signal samples in the first packet are time aligned with signal samples in the second packet;

a configuration path module configured to equalize the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

a display module coupled to the first signal module and the second signal module and configured to display the processed first packet and the processed second packet, wherein the display module is configured to display the processed first packet approximately simultaneously with the processed second packet; and

at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, the configuration path module, and the display module.

27. A computer implemented method for visualizing signals:

storing, by at least one processor executing a queueing module, a first packet in a first queue associated with a first signal, wherein the first queue enables the first packet to be processed independently;

storing, by the at least one processor executing the queueing module, a second packet in a second queue associated with a second signal, wherein the second queue enables the second packet to be processed independently;

processing, by the at least one processor executing a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;

processing, by the at least one processor executing a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;

dispatching, by the at least one processor executing a packet dispatcher module, the first packet from the first queue to the first signal module based on a global signals table;

dispatching, by the at least one processor executing the packet dispatcher module, the second packet from the second queue to the second signal module based on the global signals table;

equalizing, by the at least one processor executing a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.

28. A computer implemented method for visualizing signals:

processing, by at least one processor executing a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal based on a first tag that corresponds to a first time period, wherein the processing of the first packet incurs a first processing delay;

processing, by the at least one processor executing a second DSP of a second signal module, a second packet associated with a second signal based on a second tag that corresponds to the first time period, wherein the processing of the second packet incurs a second processing delay, and wherein signal samples in the first packet are time aligned with signal samples in the second packet;

equalizing, by the at least one processor executing a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.

29. A non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

storing, by a queueing module, a first packet in a first queue associated with a first signal, wherein the first queue enables the first packet to be processed independently;

storing, by the queueing module, a second packet in a second queue associated with a second signal, wherein the second queue enables the second packet to be processed independently;

processing, by a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;

processing, by a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;

dispatching, by a packet dispatcher module, the first packet from the first queue to the first signal module based on a global signals table;

dispatching, by the packet dispatcher module, the second packet from the second queue to the second signal module based on the global signals table;

equalizing, by a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

displaying, by a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.

30. A non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

processing, by a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal based on a first tag that corresponds to a first time period, wherein the processing of the first packet incurs a first processing delay;

processing, by a second DSP of a second signal module, a second packet associated with a second signal based on a second tag that corresponds to the first time period, wherein the processing of the second packet incurs a second processing delay, and wherein signal samples in the first packet are time aligned with signal samples in the second packet;

equalizing, by a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet; and

displaying, by a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.