Switched capacitor biasing circuit

• US 10,359,794 B2
• Filed: 10/13/2014
• Issued: 07/23/2019
• Est. Priority Date: 10/13/2014
• Status: Active Grant

• Current Assignee: Qorvo International Pte. Ltd. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Ates, Erdogan Ozgur
• Primary Examiner(s): Nguyen, Long
• Application Number:
  US15/518,071
• Publication Number:
  US 20170308106A1
• Time in Patent Office: 1,744 Days
• Field of Search: None
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

Bias circuit and a bias generator circuit comprising such a bias circuit. The bias circuit (10, 11) comprises a switched capacitor resistor circuitry (C1, C2, M12-M17), and an operational amplifier (M1-M4, M10) with an input differential transistor pair (M1, M2). The bias circuit further comprises additional source follower transistors (M5, M6) associated with the first and second input differential transistors (M1, M2).The bias generator circuit has a PMOS switched capacitor reference circuit (11) and a NMOS switched capacitor reference circuit (10) and a transconductor reference cell (15). The transconductor reference cell (15) is a replica of a basic reference cell used in a further circuit.

Claims

1. Bias circuit comprising

a switched capacitor resistor circuitry,

an operational amplifier with a first input differential transistor and a second input differential transistor coupled to form an input differential transistor pair, and an integrating capacitor connected between an output and an input of the operational amplifier,

wherein an output of the switched capacitor resistor circuitry is connected to an input of the operational amplifier,

the first input differential transistor being larger than the second input differential transistor, and

the bias circuit further comprising additional source follower transistors associated with the first and second input differential transistors.

2. Bias circuit according to claim 1, further comprising a stabilizing capacitor connected between a drain of a first input differential transistor of the operational amplifier and a ground.

3. Bias circuit according to claim 1, wherein the bias circuit is a PMOS bias generator.

4. Bias circuit according to claim 1, wherein the bias circuit is a NMOS bias generator, and further comprises additional NMOS compensating circuitry associated with the additional source follower transistors.

5. Bias circuit according to claim 2, wherein the bias circuit is a PMOS bias generator.

6. Bias circuit according to claim 2, wherein the bias circuit is a NMOS bias generator, and further comprises additional NMOS compensating circuitry associated with the additional source follower transistors.