Graphics processor sub-domain voltage regulation
First Claim
1. A system on a chip (SOC), comprising:
- an input to receive an input voltage from a source external to the SOC, wherein the input voltage is adjustable to a non-zero input voltage below 1V; and
a power domain including first sub-domain circuitry coupled to the input voltage through a first switch, and second sub-domain circuitry coupled to the input voltage through a second switch, wherein;
the first switch is to connect the first sub-domain circuitry with the input voltage in a first mode, isolate the first sub-domain circuitry from the input voltage in a second mode, and, in a third mode, reduce the input voltage down to a non-zero voltage that is output to the first sub-domain circuitry;
the second switch is to connect the second sub-domain circuitry with the input in the first mode, isolate the second sub-domain circuitry from the input in the second mode, and, in the third mode, reduce the input voltage down to a non-zero voltage that is output to the second sub-domain circuitry; and
the input voltage received is to vary at a first rate and the first switch is to change the input voltage at a second rate, faster than the first rate.
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Abstract
Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.
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Citations
18 Claims
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1. A system on a chip (SOC), comprising:
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an input to receive an input voltage from a source external to the SOC, wherein the input voltage is adjustable to a non-zero input voltage below 1V; and a power domain including first sub-domain circuitry coupled to the input voltage through a first switch, and second sub-domain circuitry coupled to the input voltage through a second switch, wherein; the first switch is to connect the first sub-domain circuitry with the input voltage in a first mode, isolate the first sub-domain circuitry from the input voltage in a second mode, and, in a third mode, reduce the input voltage down to a non-zero voltage that is output to the first sub-domain circuitry; the second switch is to connect the second sub-domain circuitry with the input in the first mode, isolate the second sub-domain circuitry from the input in the second mode, and, in the third mode, reduce the input voltage down to a non-zero voltage that is output to the second sub-domain circuitry; and the input voltage received is to vary at a first rate and the first switch is to change the input voltage at a second rate, faster than the first rate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A platform, comprising:
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a voltage regulator to provide an input voltage that is adjustable between a first non-zero input voltage and a second non-zero input voltage, at least one of which is below 1V; and a system on a chip (SOC) coupled to the voltage regulator, wherein the SOC comprises; an input to receive the input voltage from the voltage regulator; and a power domain including first sub-domain circuitry coupled to the input through a first switch, and second sub-domain circuitry coupled to the input through a second switch, wherein; the first switch is to connect the first sub-domain circuitry with the input in a first mode, isolate the first sub-domain circuitry from the input in a second mode, and, in a third mode, reduce the input voltage down to a non-zero voltage that is output to the first sub-domain circuitry; the second switch, separate from the first switch, is to connect the second sub-domain circuitry with the input in the first mode, isolate the second sub-domain circuitry from the input in the second mode, and, in a third mode, reduce the input voltage down to a non-zero voltage that is output to the second sub-domain circuitry; and the input voltage received is to vary at a first rate and the first switch is to change the input voltage at a second rate, faster than the first rate. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of operating a system on a chip (SOC), the method comprising:
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receiving an input voltage from a source external to the SOC, wherein the input voltage is adjustable to a non-zero voltage below 1V; connecting, through a first switch, first sub-domain circuitry of a power domain to the input voltage in a first mode; isolating, with the first switch, the first sub-domain circuitry from the input voltage in a second mode; and
,reducing, with the first switch, the input voltage down to a non-zero voltage output to the first sub-domain circuitry; connecting, through a second switch, second sub-domain circuitry of the power domain to the input voltage in the first mode; isolating, with the second switch, the second sub-domain circuitry from the input voltage in the second mode; and reducing, with the second switch, the input voltage down to a non-zero voltage output to the second sub-domain circuitry, wherein the input voltage received varies at a first rate and the first switch is to change the input voltage at a second rate, faster than the first rate. - View Dependent Claims (15, 16, 17, 18)
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Specification