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Graphics processor sub-domain voltage regulation

  • US 10,359,834 B2
  • Filed: 01/18/2017
  • Issued: 07/23/2019
  • Est. Priority Date: 12/19/2013
  • Status: Active Grant
First Claim
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1. A system on a chip (SOC), comprising:

  • an input to receive an input voltage from a source external to the SOC, wherein the input voltage is adjustable to a non-zero input voltage below 1V; and

    a power domain including first sub-domain circuitry coupled to the input voltage through a first switch, and second sub-domain circuitry coupled to the input voltage through a second switch, wherein;

    the first switch is to connect the first sub-domain circuitry with the input voltage in a first mode, isolate the first sub-domain circuitry from the input voltage in a second mode, and, in a third mode, reduce the input voltage down to a non-zero voltage that is output to the first sub-domain circuitry;

    the second switch is to connect the second sub-domain circuitry with the input in the first mode, isolate the second sub-domain circuitry from the input in the second mode, and, in the third mode, reduce the input voltage down to a non-zero voltage that is output to the second sub-domain circuitry; and

    the input voltage received is to vary at a first rate and the first switch is to change the input voltage at a second rate, faster than the first rate.

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