Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods

• US 10,359,933 B2
• Filed: 09/19/2016
• Issued: 07/23/2019
• Est. Priority Date: 09/19/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Muchherla, Kishore K., Malshe, Ashutosh, Ratnam, Sampath K., Feeley, Peter, Miller, Michael G., Hale, Christopher S., Padilla, Renato C.
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US15/269,518
• Publication Number:
  US 20180081543A1
• Time in Patent Office: 1,037 Days
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory having a memory controller is configured to operate a hybrid cache including a dynamic cache including x-level cell (XLC) (e.g., multi-level cell (MLC)) blocks and a static cache including single level cell (SLC) blocks. A method of operating the memory includes storing at least a portion of host data into the SLC blocks as static cache; and storing at least another portion of host data into XLC blocks in an SLC mode as dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. At least one of the static cache or dynamic cache may be disabled based on monitoring a workload of the hybrid cache relative to a Total Bytes Written (TBW) specification, such as by counting program-erase (PE) cycles of different portions of memory, or responsive to the workload exceeding a predetermined threshold defining one or more switch points.

Claims

1. A memory device, comprising:

x-level cell (XLC) blocks of non-volatile memory cells configured to be programmable with more than one bit, wherein x represents an integer greater than one;

single-level cell (SLC) blocks of non-volatile memory cells; and

a memory controller operably coupled with the XLC blocks and the SLC blocks, the memory controller configured to;

operate a hybrid cache including;

a dynamic cache including the XLC blocks of non-volatile memory cells shared between the dynamic cache and main memory; and

a static cache including the SLC blocks; and

disable at least one of the static cache or the dynamic cache so that writes to the hybrid cache are only directed to the other of the static cache or the dynamic cache based on monitoring a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the main memory over a durable lifetime for the memory device.

2. The memory device of claim 1, wherein the memory controller is configured to monitor the workload of the hybrid cache by counting program/erase (PE) cycles of the static cache.

3. The memory device of claim 1, wherein the memory controller is configured to monitor the workload of the hybrid cache by counting PE cycles of the XLC blocks being operated as dynamic cache.

4. The memory device of claim 1, wherein the memory controller is configured to monitor the workload of the hybrid cache by counting total PE cycles of the XLC blocks being operated as both main memory and dynamic cache.

5. The memory device of claim 1, wherein the memory controller is configured to disable the dynamic cache responsive to comparing PE cycles of the XLC blocks against a threshold triggering a switch point defined as a point at which operating the hybrid cache solely with the static cache ensures PE cycles of the XLC blocks remain below their maximum within the TBW Spec.

6. The memory device of claim 5, wherein the threshold increases as usage of the memory device approaches the TBW Spec.

7. The memory device of claim 1, wherein the memory controller is configured to disable the static cache responsive to comparing PE cycles of the static cache against a threshold triggering a switch point defined as a point at which operating the hybrid cache solely with the dynamic cache ensures PE cycles of the XLC blocks remain below its maximum within the TBW Spec.

8. The memory device of claim 1, wherein the XLC blocks of memory cells of the main memory and the dynamic cache are selected from the group consisting of multi-level cells (MLC), tri-level cells (TLC), and quad-level cells (QLC).

9. The memory device of claim 1, wherein the dynamic cache is configured to have a Total Bytes Written (TBW) Spec that, by itself, does not support the TBW Spec as a cache for the main memory over the durable lifetime for the memory device.

10. The memory device of claim 1, wherein the static cache is configured to have a Total Bytes Written (TBW) Spec that, by itself, does not support the TBW Spec as a cache for the XLC blocks over the durable lifetime for the memory device.

11. The memory device of claim 1, wherein the memory device is selected from the group consisting of an embedded multi-media controller, a Solid State Drive (SSD), a Universal Flash Storage (UFS) device, and a memory card.

12. The memory device of claim 1, wherein the memory controller is further configured to maintain separate host TBW counters for the static cache and the dynamic cache when monitoring the workload.

13. A memory device, comprising:

a memory array including;

single-level cell (SLC) blocks of non-volatile memory cells; and

x-level cell (XLC) blocks of non-volatile memory cells, wherein x represents an integer greater than one;

a memory controller operably coupled with the XLC blocks and the SLC blocks, the memory controller configured to;

write host data to the SLC blocks operating as a static cache in SLC mode;

write the host data to the XLC blocks operating as a dynamic cache in SLC mode if the static cache is unavailable, wherein the static cache and the dynamic cache together comprise a hybrid cache, the XLC blocks shared between the dynamic cache and main memory; and

disable at least one of the static cache or the dynamic cache so that writes to the hybrid cache are only directed to the other of the static cache or the dynamic cache based on monitoring a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the main memory over a durable lifetime for the memory device.

14. The memory device of claim 13, wherein the static cache is unavailable responsive to a workload burst of host data exceeding free space in the static cache.

15. The memory device of claim 13, wherein the static cache is unavailable responsive to the memory controller disabling the static cache from being written to.

16. The memory device of claim 13, wherein the memory controller is further configured to write the host data to the XLC blocks in XLC mode if the static cache and the dynamic cache are unavailable.

17. The memory device of claim 16, wherein the dynamic cache is unavailable responsive to the memory controller disabling the dynamic cache from being written to.

18. The memory device of claim 13, wherein the memory controller is further configured to move stored data from the static cache to XLC blocks in XLC mode during a garbage collection process.

19. The memory device of claim 18, wherein the memory controller is further configured to move stored data from the dynamic cache that was written in SLC mode to different XLC blocks in XLC mode during the garbage collection process.

20. A method of operating a memory device having a hybrid single-level cell (SLC) cache, the method comprising:

receiving host data from a host;

storing the host data in the hybrid SLC cache by;

writing the host data in SLC blocks of a static cache if the static cache is available;

writing the host data in x-level cell (XLC) blocks operating in an SLC mode as a dynamic cache if the static cache is unavailable, wherein the static cache and the dynamic cache together comprise the hybrid SLC cache, the XLC blocks shared between the dynamic cache and main memory; and

disabling at least one of the static cache or the dynamic cache so that writes to the hybrid SLC cache are only directed to the other of the static cache or the dynamic cache based on a determined workload of the hybrid SLC cache relative to a Total Bytes Written (TBW) Spec for the main memory over a durable lifetime for the memory device.

21. The method of claim 20, wherein disabling the at least one of the static cache or the dynamic cache is effective through the end of a Host Total Bytes Written (TBW) Spec for the memory device.

22. The method of claim 20, wherein storing the host data in the hybrid SLC cache further includes enabling the disabled one of the static cache or dynamic cache responsive to a reduced trend in the determined workload of the hybrid SLC cache.

23. The method of claim 20, further comprising performing garbage collection of the hybrid SLC cache by moving stored host data in at least one of the static cache or the dynamic cache to main memory in an XLC mode.

24. The method of claim 20, wherein disabling at least one of the static cache or the dynamic cache includes disabling the static cache responsive to comparing program/erase (PE) cycles consumed by the static cache against a maximum threshold for the static cache.

25. The method of claim 20, wherein disabling at least one of the static cache or the dynamic cache includes disabling the dynamic cache responsive to comparing PE cycles consumed by the XLC blocks of the memory array against a predetermined threshold of the workload for triggering a switch point.

26. The method of claim 21, wherein a predetermined threshold of the workload increases as the TBW approaches the Host TBW Spec.

27. A method of operating a memory device having a hybrid single-level cell (SLC) cache, the method comprising:

partitioning a memory array into a first portion of SLC blocks and a second portion of x-level cell (XLC) blocks;

storing at least a portion of a burst of host data into the first portion of SLC blocks as a static cache for the memory array;

storing at least another portion of the burst of host data into the second portion of XLC blocks in an SLC mode as a dynamic cache for the memory array responsive to the burst being determined to be greater than the static cache can handle, wherein the hybrid SLC cache comprises the static cache and the dynamic cache;

monitoring a workload of the hybrid cache; and

disabling at least one of the static cache or the dynamic cache so that writes to the hybrid SLC cache are only directed to the other of the static cache or the dynamic cache responsive to the workload exceeding a predetermined threshold defining one or more switch points.

28. The method of claim 27, further comprising disabling both the static cache and the dynamic cache so that attempted writes to the hybrid SLC cache are directed to XLC blocks operating in XLC mode responsive to the workload exceeding another predetermined threshold defining one or more additional switch points.

29. An electronic system, comprising:

a host device; and

a memory device operably coupled with the host device, the memory device configured to;

control writing of host data into one of a static cache, a dynamic cache, and main memory, the static cache including single-level cell (SLC) blocks of a memory array, the dynamic cache and the main memory sharing at least a portion of x-level cell (XLC) blocks of the memory array, wherein the static cache and hybrid cache together form a hybrid SLC cache; and

disable at least one of the static cache or the dynamic cache from writing host data to the hybrid cache so that writes to the hybrid SLC cache are only directed to the other of the static cache or the hybrid cache responsive to a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the main memory over a durable lifetime for the memory device exceeding a predetermined threshold defining one or more switch points,

wherein the XLC blocks include multiple bits per cell when programmed as main memory, and the XLC blocks include a single bit per cell when programmed as dynamic cache.

30. The electronic system of claim 29, further comprising at least one of an embedded multi-media controller (eMMC), a Solid State Drive (SSD), or a Universal Flash Storage (UFS) device that includes the memory device.

31. The electronic system of claim 29, further comprising one or more input devices, and one or more output devices.

32. The electronic system of claim 31, wherein the host device comprises a processor.