Cache memory system and processor system

• US 10,360,100 B2
• Filed: 09/12/2016
• Issued: 07/23/2019
• Est. Priority Date: 09/16/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Noguchi, Hiroki, Fujita, Shinobu
• Primary Examiner(s): Rizk, Samir W
• Assistant Examiner(s): Ahmed, Enam
• Application Number:
  US15/262,413
• Publication Number:
  US 20170075756A1
• Time in Patent Office: 1,044 Days
• Field of Search: 714764
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping

Abstract

A cache memory system has a nonvolatile memory which includes a first region and a second region, the first region storing readable and writable data, the second region storing an ECC for correcting an error of the data in the first region, an error corrector which generates the ECC and carries out an error correction of the data in the first region with the ECC, error rate determination circuitry which determines an error rate of the data in the first region, and region size adjustment circuitry which adjusts a size of the second region inside the nonvolatile memory based on the error rate.

Claims

1. A cache memory system, comprising:

a nonvolatile memory which includes a first region and a second region, the first region storing readable and writable data, the second region storing an ECC (Error Correcting Code) for correcting an error of the data in the first region;

an error corrector which generates the ECC and carries out an error correction of the data in the first region with the ECC;

error rate determination circuitry which determines an error rate of the data in the first region;

region size adjustment circuitry which adjusts sizes of the first region and the second region inside the nonvolatile memory so that a size of one of the first region and the second region increases and a size of another of the first region and the second region decreases based on the error rate, adjusts the size of the second region to a first size when the error rate is less than a first threshold and adjusts the size of the second region to a second size which is larger than the first size when the error rate is equal to or more than the first threshold, and writes data on a lower-level memory of the nonvolatile memory when writing the data on the first region, in a case where the error rate is equal to or more than a second threshold which is larger than the first threshold; and

an access frequency measurement circuitry which measures access frequency with respect to the second region,

wherein the region size adjustment circuitry shifts the second region inside the nonvolatile memory when the access frequency measured by the access frequency measurement circuitry reaches a predetermined frequency.

2. The cache memory system according to claim 1, wherein

the nonvolatile memory carries out readout and writing of data per cache line,

the error corrector carries out the error correction of the data per cache line,

the error rate determination circuitry determines the error rate per cache line, and

the region size adjustment circuitry adjusts the size of the second region per cache line.

3. The cache memory system according to claim 2, wherein

the nonvolatile memory has a set associative structure including a plurality of ways, each way having a data-bit width of the cache line, and

the region size adjustment circuitry adjusts the size of the second region per way in each set of the nonvolatile memory based on the error rate.

4. The cache memory system according to claim 1, comprising a controller which periodically reads out data written on the first region inside the nonvolatile memory and supplies the readout data to the error corrector, wherein

the error rate determination circuitry determines the error rate based on an error included in the data readout by the controller.

5. The cache memory system according to claim 4, wherein

the controller measures frequency of error occurrence per data in the first region, and

the error rate determination circuitry determines the error rate of each data in the first region based on the frequency of the error occurrence measured by the controller.

6. The cache memory system according to claim 1, wherein the region size adjustment circuitry shifts the second region inside the nonvolatile memory based on a predetermined condition.

7. The cache memory system according to claim 1, wherein

the nonvolatile memory comprises a data cache and a tag memory, the data cache comprising the first region and the second region, the tag memory storing address information of the data in the first region, and

the tag memory stores first information and second information, the first information indicating whether the second region is provided, and the second information specifying a position of the second region.

8. The cache memory system according to claim 7, wherein

the nonvolatile memory has a set associative structure including a plurality of ways,

the first region or the second region is set per way in each set,

the first information is provided per set, and

the second information specifies a way which is allocated to the second region.

9. The cache memory system according to claim 1, wherein the nonvolatile memory is a magnetoresistive random access memory (MRAM).

10. A processor system comprising:

a processor; and

a memory accessed by the processor,

wherein the memory comprises;

a nonvolatile memory which includes a first region and a second region, the first region storing readable and writable data, the second region storing an ECC (Error Correcting Code) for correcting an error of the data in the first region;

an error corrector which generates the ECC and carries out an error correction of the data in the first region with the ECC;

error rate determination circuitry which determines an error rate of the data in the first region;

region size adjustment circuitry which adjusts sizes of the first region and the second region inside the nonvolatile memory so that a size of one of the first region and the second region increases and a size of another of the first region and the second region decreases based on the error rate, adjusts the size of the second region to a first size when the error rate is less than a first threshold and adjusts the size of the second region to a second size which is larger than the first size when the error rate is equal to or more than the first threshold, and writes data on a lower-level memory of the nonvolatile memory when writing the data on the first region, in a case where the error rate is equal to or more than a second threshold which is larger than the first threshold; and

an access frequency measurement circuitry which measures access frequency with respect to the second region,

wherein the region size adjustment circuitry shifts the second region inside the nonvolatile memory when the access frequency measured by the access frequency measurement circuitry reaches a predetermined frequency.

11. The processor system according to claim 10, wherein

the nonvolatile memory carries out readout and writing of data per cache line,

the error corrector carries out the error correction of the data per cache line,

the error rate determination circuitry determines the error rate per cache line, and

the region size adjustment circuitry adjusts the size of the second region per cache line.

12. The processor system according to claim 11, wherein

the nonvolatile memory has a set associative structure including a plurality of ways, each way having a data-bit width of the cache line, and

the region size adjustment circuitry adjusts the size of the second region per way in each set of the nonvolatile memory based on the error rate.

13. The processor system according to claim 10, comprising a controller which periodically reads out data written on the first region inside the nonvolatile memory and supplies the readout data to the error corrector, wherein

the error rate determination circuitry determines the error rate based on an error included in the data readout by the controller.

14. The processor system according to claim 13, wherein

the controller measures frequency of error occurrence per data in the first region, and

the error rate determination circuitry determines the error rate of each data in the first region based on the frequency of the error occurrence measured by the controller.

15. The processor system according to claim 10, wherein the region size adjustment circuitry shifts the second region inside the nonvolatile memory based on a predetermined condition.