Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 10/15 and 256-symbol mapping, and bit interleaving method using same

• US 10,360,102 B2
• Filed: 05/21/2015
• Issued: 07/23/2019
• Est. Priority Date: 05/22/2014
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Park, Sung-Ik, Kwon, Sun-Hyoung, Lim, Bo-Mi, Lee, Jae-Young, Kim, Heung-Mook, Hur, Nam-Ho
• Primary Examiner(s): Britt, Cynthia
• Assistant Examiner(s): Gandhi, Dipakkumar B
• Application Number:
  US14/718,478
• Publication Number:
  US 20150339191A1
• Time in Patent Office: 1,524 Days
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/1185 wherein the parity-check matrix comprises a part with a double-diagonal
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/2778 Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Claims

1. An apparatus for transmitting a broadcast signal, the apparatus comprising:

a first memory configured to store a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15;

a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword;

a second memory configured to output the interleaved codeword;

a modulator configured to perform 256-symbol mapping corresponding to the interleaved codeword to generate a modulated signal; and

an antenna configured to broadcast a transmission signal corresponding to the modulated signal over a broadcasting channel to a reception device,

wherein the LDPC codeword is generated by performing accumulation at parity bit addresses which are updated using a predetermined sequence,

wherein the interleaving is performed using the following equation using a permutation order;

Y_j=X<sub>π

(j)</sub>0≤

j<

N_group

where X<sub>π

(j)</sub> is a π

(j)th bit group, Y_j is an interleaved j-th bit group, N_group is the number of bit groups obtained by dividing the LDPC codeword into the bit groups, and π

(j) is a permutation order for bit group-based interleaving,

wherein the permutation order corresponds to an interleaving sequence, the interleaving sequence being for the LDPC codeword having the length of 16200 and the code rate of 10/15 and being represented by the following interleaving sequence;

{28 20 18 38 39 2 3 30 19 4 14 36 7 0 25 17 10 6 33 15 8 26 42 24 11 21 23 5 40 41 29 32 37 44 43 31 35 34 22 1 16 27 9 13 12}, and

wherein the interleaved codeword is interleaved by the interleaving sequence on the bit group basis before performing the 256-symbol mapping so as to distribute burst errors occurring in the transmission signal when the transmission signal is transmitted over the broadcasting channel.

2. The apparatus of claim 1, wherein the 256-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 256 constellations.

3. The apparatus of claim 2, wherein the parallel factor is 360, and the bit group includes 360 bits.

4. The apparatus of claim 3, wherein the LDPC codeword is represented by (u₀, u₁, . . . , u_Nldpc−

1) (where N_ldpc is

     16200), and is divided into 45 bit groups each including 360 bits, as in the following equation;

X_j={u_k|360×

j≤

k<

360×

(j+1),0≤

k<

N_ldpc} for 0≤

j<

N_group

where X_j is a j-th bit group, N_ldpc is 16200, and N_group is 45.