ECC memory controller to detect dangling pointers

• US 10,360,104 B2
• Filed: 05/08/2017
• Issued: 07/23/2019
• Est. Priority Date: 05/08/2017
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: David, Thomas S.
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US15/589,217
• Publication Number:
  US 20180321875A1
• Time in Patent Office: 806 Days
• Field of Search: 714763, 714767, 714766
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: H03M 13/13 Linear codes

Abstract

A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

Claims

1. A system for detecting dangling pointers, comprising:

an ECC memory controller in communication with a data memory and an ECC memory;

wherein the ECC memory controller comprises a state machine, wherein the state machine writes an erroneous data word to the data memory at a data address and an erroneous ECC syndrome to the ECC memory at the data address.

2. The system of claim 1, wherein the state machine comprises a starting address register to store a starting address and a second register to indicate a number of data addresses to be written.

3. The system of claim 2, wherein the state machine repeats steps of:

incrementing the data address after writing the erroneous data word and the erroneous ECC syndrome; and

writing the erroneous data word to the data memory and the erroneous ECC syndrome to the ECC memory at the data address;

until the number of data addresses has been written.

4. The system of claim 2, wherein the second register comprises a word count register.

5. The system of claim 2, wherein the second register comprises an ending address register.

6. The system of claim 1, wherein the erroneous data word and the erroneous ECC syndrome are written to denote that memory at the data address has been freed.

7. The system of claim 6, wherein an ECC error is indicated if a freed memory location is read.

8. A method of detecting dangling pointers, comprising:

writing erroneous data word to a data memory and an erroneous ECC syndrome to an ECC memory at a memory address using an ECC memory controller, where the erroneous data word and erroneous ECC syndrome are selected to as to generate an ECC error; and

reading the erroneous data word and the erroneous ECC syndrome at the memory address at a later time; and

generating an ECC error after the reading.

9. The method of claim 8, wherein a state machine is disposed in the ECC memory controller, the ECC memory controller adapted to be in communication with a data memory and an ECC memory, the method further comprising, prior to the writing:

loading a starting address into a starting address register in the state machine;

providing an indication of a word count to the state machine; and

using the starting address as a memory address.

10. The method of claim 9, further comprising:

incrementing the memory address after the writing;

incrementing a counter after the writing; and

repeating the writing and incrementing steps if the counter is less than the word count.

11. The method of claim 9, wherein providing an indication of the word count comprising writing the word count to a word count register in the state machine.

12. The method of claim 9, wherein providing an indication of the word count comprising writing a second address to an ending address register in the state machine.

13. A system for detecting dangling pointers, comprising:

an ECC memory controller in communication with a data memory and an ECC memory;

wherein the ECC memory controller comprises a state machine, wherein the state machine reads a syndrome stored in the ECC memory at an ECC address, corrupts the syndrome by inverting at least one bit, and writes the corrupted syndrome back to the ECC memory at the ECC address.

14. The system of claim 13, wherein the state machine comprises a starting address register to store the starting address and a second register to indicate a number of syndromes that are to be corrupted, and wherein the ECC address is initialized to the starting address.

15. The system of claim 14, wherein the state machine repeats steps of:

incrementing the ECC address after writing the corrupted syndrome;

reading a syndrome stored in the ECC memory at the ECC address;

corrupting the syndrome by inverting at least one bit; and

writing the corrupted syndrome back to the ECC memory at the ECC address;

until the number of syndromes has been corrupted.

16. The system of claim 14, wherein the second register comprises a word count register.

17. The system of claim 14, wherein the second register comprises an ending address register.

18. A system for detecting dangling pointers, comprising:

an ECC memory controller in communication with a data memory and an ECC memory;

wherein the ECC memory controller comprises a state machine, wherein the state machine reads a data word stored in the data memory at a data address, corrupts the data word by inverting at least one bit, and writes the corrupted data word back to the data memory at the data address.

19. The system of claim 18, wherein the state machine comprises a starting address register to store the starting address and a second register to indicate a number of words that are to be corrupted, and wherein the data address is initialized to the starting address.

20. The system of claim 19, wherein the state machine repeats steps of:

incrementing the data address after writing the corrupted data word;

reading a data word stored in the data memory at the data address;

corrupting the data word by inverting at least one bit; and

writing the corrupted data word back to the data memory at the data address;

until the number of data words has been corrupted.

21. The system of claim 19, wherein the second register comprises a word count register.

22. The system of claim 19, wherein the second register comprises an ending address register.