Asynchronous interface

• US 10,360,169 B2
• Filed: 02/19/2016
• Issued: 07/23/2019
• Est. Priority Date: 03/30/2015
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Inventors: Kumata, Ichiro
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Daley, Christopher
• Application Number:
  US15/560,336
• Publication Number:
  US 20180074991A1
• Time in Patent Office: 1,250 Days
• CPC Class Codes: G06F 13/4036 and deadlock prevention
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4213 with asynchronous protocol
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 2213/0004 Parallel ports, e.g. centronics
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

An asynchronous interface according to the disclosure includes: a transmission circuit that transmits, with data of W bits as one word, the data on the one-word basis, and transmits an REQ signal whose value differs by one bit per transmission of the data of one word; a reception circuit including a reception buffer having a reception buffer word count of n (n is an integer of 4 or more), in which the reception circuit receives the data on the one-word basis, and transmits an ACK signal whose value differs by one bit per reception of the data of one word; a data signal line that has a bit width of W, and transfers the data from the transmission circuit to the reception circuit; an REQ signal line that has a bit width of log₂ (n) or more, and transfers the REQ signal from the transmission circuit to the reception circuit; and an ACK signal line that has a bit width of log₂(n) or more, and transfers the ACK signal from the reception circuit to the transmission circuit.

Claims

1. An asynchronous interface, comprising:

a transmission circuit configured to;

transmit, with data of W bits data on a one-word basis, wherein

W is an integer greater than or equal to 1; and

transmit an REQ signal a value of which differs by one bit per transmission of the data of one word;

a reception circuit that comprises a reception buffer, wherein a reception buffer word count of the reception buffer is n, n is an integer of 4 or more, and

the reception circuit is configured to;

receive the data on the one-word basis from the transmission circuit, and

transmit an ACK signal to the transmission circuit,

wherein a value of the ACK signal differs by one bit per reception of the data of one word;

a data signal line configured to transfer the data from the transmission circuit to the reception circuit,

wherein a first bit width of the data signal line is W;

an REQ signal line a bit width of which is log₂ (n) or more, the REQ signal line is configured to transfer the REQ signal from the transmission circuit to the reception circuit; and

an ACK signal line a bit width of which is log₂ (n) or more, the ACK signal line is configured to transfer the ACK signal from the reception circuit to the transmission circuit.

2. The asynchronous interface according to claim 1, wherein

the transmission circuit is further configured to transmit, with respect to successive n times of data transmission, the REQ signal n times, with the value of the REQ signal differing each time, and

the reception circuit is further configured to transmit, with respect to successive n times of data reception, the ACK signal n times, with the value of the ACK signal differing each time.

3. The asynchronous interface according to claim 1, wherein

the reception circuit is further configured to:

write the data received, on the one-word basis, to the reception buffer with utilization of the REQ signal as a write address, and read the data in the reception buffer, on the one-word basis, with utilization of the ACK signal as a read address.

4. The asynchronous interface according to claim 1, wherein

a sum of signal propagation time in which the REQ signal is propagated through the REQ signal line and signal propagation time in which the ACK signal is propagated through the ACK signal line is larger than a minimum cycle it takes for the transmission circuit to transmit the data or a minimum cycle it takes for the reception circuit to receive the data.

5. The asynchronous interface according to claim 4, wherein

Ta represents time it takes for the transmission circuit to transmit the data of one word and the REQ signal, for the reception circuit to transmit the ACK signal in response thereto, for the transmission circuit to receive the ACK signal, and for the transmission circuit to determine whether or not next data transmission is possible,

Tb represents whichever cycle is larger, out of a transmission clock cycle of the transmission circuit and a reception clock cycle of the reception circuit, and

the following relation is satisfied,

n×

Tb≥

Ta.

6. The asynchronous interface according to claim 1, wherein

the data signal line having the bit width of one word is provided in two or more systems, and

the transmission circuit is further configured to:

allocate the data of a plurality of words, on the one-word basis, to data signal lines of the two or more systems, and transmit the data of the plurality of words, to allow transmission timing to differ from one another.

7. The asynchronous interface according to claim 1, wherein

the reception buffer word count n is a power of 2 and is equal to or larger than 8, and

the bit width of each of the REQ signal line and the ACK signal line is log₂(n).