Fast track routing of streaming data using FPGA devices

• US 10,360,632 B2
• Filed: 12/28/2018
• Issued: 07/23/2019
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Ip Reservoir, LLC
• Inventors: Parsons, Scott, Taylor, David E., Schuehler, David Vincent, Franklin, Mark A., Chamberlain, Roger D.
• Primary Examiner(s): Borlinghaus, Jason
• Application Number:
  US16/234,982
• Publication Number:
  US 20190139138A1
• Time in Patent Office: 207 Days
• Field of Search: None
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

Systems and methods are disclosed for fast track routing of streaming data as between multiple compute resources. For example, the system may comprise a processor, reconfigurable logic device, a shared memory that is mapped into a kernel and user space of an operating system for the processor, a network protocol stack, and driver code for execution within the kernel space of the operating system while the operating system is in the kernel mode. The driver code can be configured to (1) maintain a kernel level interface into the network protocol stack, (2) copy the streaming data from the network protocol stack into the shared memory, wherein the copy operation is performed by the driver code without the operating system transitioning to the user mode, and (3) facilitate DMA transfers of data from the shared memory into the reconfigurable logic device for processing thereby.

Claims

1. A system for fast track routing of streaming data as between multiple compute resources, the system comprising:

a processor configured to execute an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode;

a reconfigurable logic device;

a shared memory that is mapped into the kernel space and the user space of the operating system;

a network protocol stack for execution by the operating system, wherein the network protocol stack is configured to receive streaming data; and

driver code for execution within the kernel space of the operating system while the operating system is in the kernel mode, the driver code configured to (1) maintain a kernel level interface into the network protocol stack, (2) copy the streaming data from the network protocol stack into the shared memory, wherein the copy operation is performed by the driver code without the operating system transitioning to the user mode, and (3) facilitate DMA transfers of data from the shared memory into the reconfigurable logic device for processing thereby.

2. The system of claim 1 wherein the driver code comprises:

a first driver for execution within the kernel space of the operating system while the operating system is in the kernel mode, the first driver configured to (1) maintain the kernel level interface into the network protocol stack, and (2) copy the streaming data from the network protocol stack into the shared memory, wherein the copy operation is performed by the first driver without the operating system transitioning to the user mode; and

a second driver for execution within the kernel space of the operating system while the operating system is in the kernel mode, the second driver configured to facilitate the DMA transfers of data from the shared memory into the reconfigurable logic device for processing thereby.

3. The system of claim 2 wherein the shared memory comprises (1) a first shared memory that is mapped into the kernel space and the user space of the operating system, and (2) a second shared memory that is mapped into the kernel space and the user space of the operating system;

wherein the system further comprises user mode code for execution within the user space of the operating system, the user mode code configured to (i) access data from the first shared memory without the operating system transitioning to the kernel mode, (ii) process the accessed data, and (iii) write the processed data to the second shared memory; and

wherein the second driver is configured to facilitate the DMA transfers of data from the second shared memory into the reconfigurable logic device for processing thereby.

4. The system of claim 3 wherein the processor comprises a multi-core processor.

5. The system of claim 4 wherein the user mode code comprises a plurality of processing threads for execution by cores of the multi-core processor.

6. The system of claim 3 wherein the user mode code is configured to normalize the streaming data and write the normalized data into the second shared memory.

7. The system of claim 3 wherein the first shared memory comprises a ring buffer, and wherein the second shared memory comprises a ring buffer.

8. The system of claim 2 wherein the shared memory comprises (1) a first shared memory that is mapped into the kernel space and the user space of the operating system, and (2) a second shared memory that is mapped into the kernel space and the user space of the operating system;

wherein the processor is loadable with user mode code for execution within the user space of the operating system;

wherein the first shared memory is readable by the user mode code without the operating system transitioning to the kernel mode;

wherein the second shared memory is writeable by the user mode code; and

wherein the second driver is configured to facilitate the DMA transfers of data from the second shared memory into the reconfigurable logic device for processing thereby.

9. The system of claim 8 further comprising the user mode code.

10. The system of claim 2 wherein the second driver is further configured to update a plurality of descriptor tables for facilitating the DMA transfers into the reconfigurable logic device.

11. The system of claim 1 wherein the shared memory comprises a ring buffer.

12. The system of claim 1 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

13. The system of claim 1 wherein the reconfigurable logic device comprises a firmware socket that receives data via the DMA transfers from the shared memory and streams the received data into the reconfigurable logic device for processing thereby.

14. The system of claim 13 wherein the reconfigurable logic device further comprises a processing pipeline that processes the streaming data from the firmware socket.

15. The system of claim 1 further comprising:

another memory, wherein the another memory is in the kernel space of the operating system;

additional driver code for execution within the kernel space of the operating system;

wherein the reconfigurable logic device is further configured to stream data into the another memory via DMA transfers; and

wherein the additional driver code is configured to read the data from the another memory.

16. The system of claim 15 wherein the additional driver code is further configured to communicate the read data for delivery to a consumer.

17. The system of claim 16 wherein the additional driver code is further configured to communicate the read data to the consumer via the network protocol stack.

18. The system of claim 17 wherein the additional driver code is further configured to (1) maintain a kernel level interface into the network protocol stack, and (2) communicate the read data to the network protocol stack without the operating system transitioning to the user mode.

19. The system of claim 16 wherein the additional driver code comprises:

a first driver for execution within the kernel space of the operating system while the operating system is in the kernel mode, the first driver configured to read the DMA-transferred data from the another memory; and

a second driver for execution within the kernel space of the operating system while the operating system is in the kernel mode, the second driver configured to (1) maintain a kernel level interface into the network protocol stack, and (2) communicate the read data to the network protocol stack without the operating system transitioning to the user mode.

20. A system for fast track routing of streaming data as between multiple compute resources, the system comprising:

a processor configured to execute an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode;

a reconfigurable logic device;

a shared memory that is mapped into the kernel space and the user space of the operating system, wherein the shared memory comprises a first buffer and a second buffer, the first buffer for storing data that is available for processing from the user mode of the operating system, the second buffer for storing data that is for direct transfer into the reconfigurable logic device;

additional memory in the kernel space of the operating system;

a network protocol stack for execution by the operating system, wherein the network protocol stack is configured to receive streaming data; and

driver code for execution within the kernel space of the operating system while the operating system is in the kernel mode;

wherein the driver code is configured to maintain a kernel level interface into the network protocol stack;

wherein the driver code is further configured to copy streaming data from the network protocol stack into the first buffer to make the copied streaming data instantly accessible to the user mode of the operating system, wherein the copy operation is performed by the driver code without the operating system transitioning to the user mode; and

wherein the driver code and the reconfigurable logic device are configured to cooperate with each other to stream data through the reconfigurable logic device via DMA transfers (1) from the second buffer into the reconfigurable logic device, and (2) from the reconfigurable logic device into the additional memory.

21. The system of claim 20 wherein the first buffer comprises a ring buffer, and wherein the second buffer comprises a ring buffer.

22. The system of claim 21 wherein the processor comprises a multi-core processor, and wherein the first buffer comprises a plurality of ring buffers for storing data that is instantly accessible to different cores of the multi-core processor.

23. The system of claim 20 wherein the driver code comprises:

a first driver for execution within the kernel space of the operating system while the operating system is in the kernel mode, the first driver configured to (1) maintain the kernel level interface into the network protocol stack, and (2) copy streaming data from the network protocol stack into the first buffer to make the copied streaming data instantly accessible to the user mode of the operating system, wherein the copy operation is performed by the first driver without the operating system transitioning to the user mode; and

a second driver for execution within the kernel space of the operating system while the operating system is in the kernel mode, the second driver configured to facilitate the DMA transfers of data from the second buffer into the reconfigurable logic device for processing thereby.

24. The system of claim 20 further comprising:

user mode code for execution within the user space of the operating system, the user mode code configured to (i) access data in the first buffer without the operating system transitioning to the kernel mode, (ii) process the accessed data, and (iii) write the processed data to the second buffer.

25. The system of claim 20 wherein the driver code is further configured to communicate outgoing data from the additional memory to the network protocol stack without the operating system transitioning to the user mode.