Distributed pulse-width modulation system with multi-bit digital storage and output device
First Claim
1. A distributed pulse-width modulation system, comprising:
- an array of pulse-width modulation elements, wherein each element of the array comprises;
a cycle counter,a digital memory for storing a plurality of multi-bit digital values, the multi-bit digital values all having the same number of bits,a drive circuit for each stored multi-bit digital value, andan output device for each stored multi-bit digital value,wherein, for each stored multi-bit digital value, the corresponding drive circuit drives the corresponding output device in response-to the multi-bit digital value stored in the digital memory; and
a system controller including a memory for storing the plurality of multi-bit digital values for each pulse-width modulation element and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element,wherein each element of the array comprises a pulse-width modulation (PWM) counter with a counter output having as many bits as the number of bits in the multi-bit digital values and a comparator circuit for each stored multi-bit digital value, wherein each comparator circuit compares the counter output to the corresponding multi-bit digital value, and wherein each drive circuit is responsive to the output of the corresponding comparator circuit, andwherein the cycle counter is separate from the PWM counter or the cycle counter and the PWM counter are part of a common counter, the PWM counter operates with the cycle counter to provide multiple cycles of PWM timing signals for the multi-bit digital values, the drive circuit comprises an output state indicating whether the output is off or on, and the drive circuit comprises circuitry to set the output state to the off state when the PWM counter is equal to zero.
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Abstract
A distributed pulse-width modulation system includes an array of pulse-width modulation elements, each element including a digital memory for storing a plurality of multi-bit digital values, a drive circuit for each stored multi-bit digital value, and an output device for each stored multi-bit digital value. The multi-bit digital values all have the same number of bits. For each stored multi-bit digital value, the corresponding drive circuit drives the corresponding output device in response to the multi-bit digital value stored in the digital memory. A system controller includes a memory for storing the multi-bit digital values for each pulse-width modulation element and a communication circuit communicates each multi-bit digital value to each corresponding pulse-width modulation element.
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Citations
10 Claims
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1. A distributed pulse-width modulation system, comprising:
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an array of pulse-width modulation elements, wherein each element of the array comprises; a cycle counter, a digital memory for storing a plurality of multi-bit digital values, the multi-bit digital values all having the same number of bits, a drive circuit for each stored multi-bit digital value, and an output device for each stored multi-bit digital value, wherein, for each stored multi-bit digital value, the corresponding drive circuit drives the corresponding output device in response-to the multi-bit digital value stored in the digital memory; and a system controller including a memory for storing the plurality of multi-bit digital values for each pulse-width modulation element and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element, wherein each element of the array comprises a pulse-width modulation (PWM) counter with a counter output having as many bits as the number of bits in the multi-bit digital values and a comparator circuit for each stored multi-bit digital value, wherein each comparator circuit compares the counter output to the corresponding multi-bit digital value, and wherein each drive circuit is responsive to the output of the corresponding comparator circuit, and wherein the cycle counter is separate from the PWM counter or the cycle counter and the PWM counter are part of a common counter, the PWM counter operates with the cycle counter to provide multiple cycles of PWM timing signals for the multi-bit digital values, the drive circuit comprises an output state indicating whether the output is off or on, and the drive circuit comprises circuitry to set the output state to the off state when the PWM counter is equal to zero. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification