Distributed pulse-width modulation system with multi-bit digital storage and output device

• US 10,360,846 B2
• Filed: 05/09/2017
• Issued: 07/23/2019
• Est. Priority Date: 05/10/2016
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Cok, Ronald S., Rotzoll, Robert R.
• Primary Examiner(s): Lin, Chun-Nan
• Application Number:
  US15/590,827
• Publication Number:
  US 20170330509A1
• Time in Patent Office: 805 Days
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3225 using an active matrix

Abstract

A distributed pulse-width modulation system includes an array of pulse-width modulation elements, each element including a digital memory for storing a plurality of multi-bit digital values, a drive circuit for each stored multi-bit digital value, and an output device for each stored multi-bit digital value. The multi-bit digital values all have the same number of bits. For each stored multi-bit digital value, the corresponding drive circuit drives the corresponding output device in response to the multi-bit digital value stored in the digital memory. A system controller includes a memory for storing the multi-bit digital values for each pulse-width modulation element and a communication circuit communicates each multi-bit digital value to each corresponding pulse-width modulation element.

Claims

1. A distributed pulse-width modulation system, comprising:

an array of pulse-width modulation elements, wherein each element of the array comprises;

a cycle counter,

a digital memory for storing a plurality of multi-bit digital values, the multi-bit digital values all having the same number of bits,

a drive circuit for each stored multi-bit digital value, and

an output device for each stored multi-bit digital value,

wherein, for each stored multi-bit digital value, the corresponding drive circuit drives the corresponding output device in response-to the multi-bit digital value stored in the digital memory; and

a system controller including a memory for storing the plurality of multi-bit digital values for each pulse-width modulation element and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element,

wherein each element of the array comprises a pulse-width modulation (PWM) counter with a counter output having as many bits as the number of bits in the multi-bit digital values and a comparator circuit for each stored multi-bit digital value, wherein each comparator circuit compares the counter output to the corresponding multi-bit digital value, and wherein each drive circuit is responsive to the output of the corresponding comparator circuit, and

wherein the cycle counter is separate from the PWM counter or the cycle counter and the PWM counter are part of a common counter, the PWM counter operates with the cycle counter to provide multiple cycles of PWM timing signals for the multi-bit digital values, the drive circuit comprises an output state indicating whether the output is off or on, and the drive circuit comprises circuitry to set the output state to the off state when the PWM counter is equal to zero.

2. The system of claim 1, wherein the system controller includes a timing circuit for providing timing signals to each element and wherein the timing signals control the rate at which the output devices are driven in response to the multi-bit digital values stored in the digital memory.

3. The system of claim 1, wherein the comparator circuit is a parallel comparator circuit.

4. The system of claim 1, wherein the comparator circuit is a serial comparator circuit.

5. The system of claim 1, wherein the drive circuit comprises an output state indicating whether the output is off or on and the drive circuit drives the output device to output a signal when the output state is on and drives the output device such that the output device does not output a signal when the output state is off.

6. The system of claim 5, wherein the drive circuit drives the output device to output a signal in a constant state over time when the output state is on.

7. The system of claim 6, wherein the signal is an electrical signal and the constant state comprises at least one of a constant current and a constant voltage.

8. The system of claim 1, wherein the comparator circuit comprises an exclusive NOR combination of at least a portion of the bits of the counter value and the bits of the corresponding multi-bit digital value.

9. The system of claim 1, wherein the digital memory is a register, a random access memory, or a content addressable memory.

10. The system of claim 1, wherein the output device is a light emitter, a light-emitting diode, an inorganic light-emitting diode, or a micro-light-emitting diode.