Displays with supplemental loading structures

• US 10,360,862 B2
• Filed: 05/15/2018
• Issued: 07/23/2019
• Est. Priority Date: 09/07/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Yeh, Shin-Hung, Jamshidi Roudbari, Abbas, Chang, Ting-Kuo
• Primary Examiner(s): Lee, Benjamin C
• Assistant Examiner(s): Neupane, Krishna P
• Application Number:
  US15/980,437
• Publication Number:
  US 20190073976A1
• Time in Patent Office: 434 Days
• Field of Search: None
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0478 related to liquid crystal pixels
• CPC Class Codes: G09G 2310/0264 Details of driving circuits
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/002 to project the image of a two-dimensional display, such as an array of light emitting or modulating elements or a CRT
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3666 with the matrix divided into sections
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

Claims

1. A display having an active area from which light is emitted and an inactive area that does not emit light, comprising:

an array of pixels;

display driver circuitry;

data lines coupled to the display driver circuitry;

gate lines coupled to the display driver circuitry, wherein the gate lines include first and second gate lines and wherein the first gate line is coupled to fewer pixels than the second gate line;

a supplemental gate line loading structure in the inactive area of the display, wherein the supplemental gate line loading structure increases loading on the first gate line; and

a bias voltage supply line that biases the supplemental gate line loading structures.

2. The display defined in claim 1 wherein the supplemental loading structure comprises doped polysilicon.

3. The display defined in claim 2 further comprising a transparent conductive layer that overlaps the doped polysilicon.

4. The display defined in claim 3 further comprising a via that electrically couples the transparent conductive layer to the doped polysilicon.

5. The display defined in claim 4 wherein the transparent conductive layer is coupled to the bias voltage supply line.

6. The display defined in claim 5 wherein the bias voltage supply line comprises multiple metal layers.

7. The display defined in claim 5 wherein the doped polysilicon has an H-shape with two vertical segments connected by a horizontal segment.

8. The display defined in claim 7 wherein the via is coupled to the horizontal segment.

9. The display defined in claim 8 wherein the two vertical segments overlap the first gate line.

10. The display defined in claim 3 wherein the pixels comprise a common voltage layer, and wherein the transparent conductive layer is formed from the same material as the common voltage layer.

11. The display defined in claim 10 wherein the pixels comprise transistors with polysilicon channels, and wherein the doped polysilicon is formed from the same material as the polysilicon channels.

12. The display defined in claim 1 wherein the gate lines include a third gate line coupled to fewer pixels than the second gate line, wherein the supplemental gate line loading structure increases loading on the third gate line.

13. The display defined in claim 1 wherein some of the data lines overlap the first gate line in the inactive area of the display.

14. The display defined in claim 1 further comprising a metal layer that electrically couples the supplemental gate line loading structures to the bias voltage supply line.

15. The display defined in claim 14 further wherein the metal layer is formed from the same material as the data lines.

16. A display having an active area and an inactive area, comprising:

an array of pixels in the active area, wherein the array of pixels includes first and second rows and wherein the first row has fewer pixels than the second row;

gate lines coupled to the array of pixels, wherein the gate lines include a first gate line coupled to the first row of pixels and a second gate line coupled to the second row of pixels, and wherein the first gate line has a segment in the inactive area;

dummy pixels in the inactive area that do not emit light, wherein the dummy pixels comprise doped polysilicon that overlaps the segment of the first gate line in the inactive area to increase loading on the first gate line; and

a metal layer that electrically couples the dummy pixels to a bias voltage supply line.

17. The display defined in claim 16 further comprising data lines coupled to the array of pixels, wherein the metal layer is formed from the same material as the data lines.

18. The display defined in claim 17 wherein the dummy pixels comprise extended portions of the data lines.

19. A display having an active area and an inactive area, comprising;

an array of pixels in the active area;

a common voltage layer comprising row electrodes and column electrodes, wherein the common voltage layer is configured to serve as a ground plane for the array of pixels in a first mode and to gather touch data in a second mode;

rows of signal lines respectively coupled to the row electrodes, wherein the rows of signal lines include first and second signal lines, and wherein the first signal line is coupled to fewer row electrodes than the second signal line; and

a conductive layer in the inactive area that overlaps the first signal line to increase loading on the first signal line.

20. The display defined in claim 19 wherein the conductive layer comprises indium tin oxide.

21. The display defined in claim 19 further comprising:

gate lines coupled to the array of pixels, wherein the gate lines include first and second gate lines, wherein the first gate line is coupled to fewer pixels than the second gate line, and wherein the first gate line overlaps the conductive layer in the inactive area; and

gate line loading structures in the inactive area of the display that increase loading on the first gate line.

22. The display defined in claim 21 wherein the gate line loading structures include data lines and doped polysilicon that overlap the first gate line in the inactive area.