NAND cell encoding to improve data integrity

• US 10,360,947 B2
• Filed: 08/31/2017
• Issued: 07/23/2019
• Est. Priority Date: 08/31/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Stichka, Tyson M., Thomson, Preston, Stoller, Scott Anthony, Bueb, Christopher, Huang, Jianmin, Tanpairoj, Kulachet, Singidi, Harish
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/692,508
• Publication Number:
  US 20190066736A1
• Time in Patent Office: 691 Days
• Field of Search: 36518509, 36518518
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

Claims

1. A NAND device for NAND cell encoding, the NAND device comprising:

a NAND cell; and

a controller to;

obtain a high-temperature indicator;

receive a write operation; and

perform the write operation on a NAND cell using a modified encoding in response to the high-temperature indicator, the modified encoding including a reduced number of voltage distribution positions, resulting in fewer bits stored for each cell, from an unmodified encoding without changing voltage distribution widths, the position of a voltage distribution is defined as a central tendency of a range of voltages bounded by values within half of a width of the central tendency, each voltage distribution corresponding to a discrete set of states in an encoding.

2. The NAND device of claim 1, wherein the modified encoding includes a different voltage distribution position from a first position unmodified the encoding to a second position in the modified encoding.

3. The NAND device of claim 2, wherein the second position is within a defined range of voltages.

4. The NAND device of claim 2, wherein the range of voltages is defined by a read voltage for a state in the discrete set of states for the unmodified encoding that corresponds to the voltage distribution position.

5. The NAND device of claim 2, wherein the second position increases a read margin for the voltage distribution.

6. The NAND device of claim 1, wherein the unmodified encoding has eight discrete states.

7. The NAND device of claim 6, wherein the modified encoding has four discrete states.

8. The NAND device of claim 7, wherein the write operation is performed in two passes, the first pass operating in accordance with parameters of the unmodified encoding, and the second pass operating to enact the modified encoding.

9. The NAND device of claim 8, wherein the four discrete states correspond to states three, four, and seven from the eight discrete states, the states ordered by voltage from lower to higher.

10. The NAND device of claim 1, wherein the controller is arranged to perform a read operation on the NAND cell using the unmodified encoding.

11. The NAND device of claim 1, wherein the controller is arranged to:

obtain a clearance of the high-temperature indicator;

perform maintenance on the NAND cell to free the NAND cell for another write operation;

receive a second write operation; and

perform the second write operation on the NAND cell using the unmodified encoding in response to clearance of the high-temperature indicator.

12. A method for NAND cell encoding, the method comprising:

obtaining a high-temperature indicator;

receiving a write operation; and

performing the write operation on a NAND cell using a modified encoding in response to the high-temperature indicator, the modified encoding including a reduced number of voltage distribution positions, resulting in fewer bits stored for each cell, from an unmodified encoding without changing voltage distribution widths, the position of a voltage distribution is defined as a central tendency of a range of voltages bounded by values within half of a width of the central tendency, each voltage distribution corresponding to a discrete set of states in an encoding.

13. The method of claim 12, wherein the modified encoding includes changing a voltage distribution position from a first position in the unmodified encoding to a second position in the modified encoding.

14. The method of claim 13, wherein the second position is within a defined range of voltages.

15. The method of claim 13, wherein the range of voltages is defined by a read voltage for a state in the discrete set of states for the unmodified encoding that corresponds to the voltage distribution position.

16. The method of claim 13, wherein the second position increases a read margin for the voltage distribution.

17. The method of claim 12, wherein the unmodified encoding has eight discrete states.

18. The method of claim 17, wherein the modified encoding has four discrete states.

19. The method of claim 18, wherein the write operation is performed in two passes, the first pass operating in accordance with parameters of the unmodified encoding, and the second pass operating to enact the modified encoding.

20. The method of claim 19, wherein the four discrete states correspond to states three, four, and seven from the eight discrete states, the states ordered by voltage from lower to higher.

21. The method of claim 12, comprising performing a read operation on the NAND cell using the unmodified encoding.

22. The method of claim 12, comprising:

obtaining a clearance of the high-temperature indicator;

performing maintenance on the NAND cell to free the NAND cell for another write operation;

receiving a second write operation; and

performing the second write operation on the NAND cell using the unmodified encoding in response to clearance of the high-temperature indicator.

23. At least one machine readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:

obtaining a high-temperature indicator;

receiving a write operation; and

performing the write operation on a NAND cell using a modified encoding in response to the high-temperature indicator, the modified encoding including a reduced number of voltage distribution positions, resulting in fewer bits stored for each cell, from an unmodified encoding without changing voltage distribution widths, the position of a voltage distribution is defined as a central tendency of a range of voltages hounded by values within half of a width of the central tendency, each voltage distribution corresponding to a discrete set of states in an encoding.

24. The machine readable medium of claim 23, wherein the modified encoding includes changing a voltage distribution position from a first position in the unmodified encoding to a second position in the modified encoding.

25. The machine readable medium f claim 24, wherein the second position is within a defined range of voltages.

26. The machine readable medium of claim 24, wherein the range of voltages is defined by a read voltage for a state in the discrete set of states for the unmodified encoding that corresponds to the voltage distribution position.

27. The machine readable medium of claim 24, wherein the second position increases a read margin for the voltage distribution.

28. The machine readable medium of claim 23, wherein the unmodified encoding has eight discrete states.

29. The machine readable medium of claim 28, wherein the modified encoding has four discrete states.

30. The machine readable medium of claim 29, wherein the operation is performed in two passes, the first pass operating in accordance with parameters of the unmodified encoding, and the second pass operating to enact the modified encoding.

31. The machine readable medium of claim 30, wherein the four discrete states correspond to states three, four, and seven from the eight discrete states, the states ordered by voltage from lower to higher.

32. The machine readable medium of claim 23, wherein the operations comprise performing a read operation on the NAND cell using the unmodified encoding.

33. The machine readable medium of claim 23, wherein e operations comprise:

obtaining a clearance of the high-temperature indicator;

performing maintenance on the NAND cell to free the NAND cell for another write operation;

receiving a second write operation; and

performing the second write operation on the NAND cell using the unmodified encoding in response to clearance of the high-temperature indicator.