Methods and structures for forming uniform fins when using hardmask patterns

• US 10,361,125 B2
• Filed: 12/19/2017
• Issued: 07/23/2019
• Est. Priority Date: 12/19/2017
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Xu, Peng, Cheng, Kangguo, Mignot, Yann, Lee, Choonghyun
• Primary Examiner(s): Ngo, Ngan V
• Application Number:
  US15/846,844
• Publication Number:
  US 20190189519A1
• Time in Patent Office: 581 Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a hardmask layer on a substrate;

patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate;

depositing a dummy hardmask layer on the substrate;

patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions;

transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate; and

forming a spacer layer on the dummy hardmask layer.

2. The method according to claim 1, wherein a distance between a patterned dummy hardmask portion and an adjacent outermost patterned hardmask portion is the same or substantially the same as a distance between two adjacent patterned hardmask portions.

3. The method according to claim 1, wherein a width of a patterned dummy hardmask portion is the same or substantially the same as a width of a patterned hardmask portion.

4. The method according to claim 1, further comprising removing portions of the spacer layer to form a plurality of spacers on the dummy hardmask layer.

5. The method according to claim 4, wherein a width of a spacer of the plurality of spacers is the same or substantially the same as a width of a patterned hardmask portion.

6. The method according to claim 4, wherein the plurality of spacers cover portions of the dummy hardmask layer, and wherein the patterning of the dummy hardmask layer comprises removing remaining portions of the dummy hardmask layer not covered by the plurality of spacers.

7. The method according to claim 6, further comprising removing the plurality of spacers from the plurality of patterned dummy hardmask portions.

8. The method according to claim 1, wherein the plurality of patterned hardmask portions and patterned dummy hardmask portions cover portions of the substrate and the transferring comprises etching remaining portions of the substrate not covered by the plurality of patterned hardmask portions and patterned dummy hardmask portions to form the plurality of fins and dummy fins.

9. The method according to claim 8, wherein the etching is performed to a depth including an active height of the plurality of fins.

10. The method according to claim 9, further comprising removing the plurality of patterned dummy hardmask portions from the plurality of dummy fins.

11. The method according to claim 10, further comprising further etching remaining portions of the substrate not covered by the plurality of patterned hardmask portions, including the plurality of dummy fins to a depth below the active height of the plurality of fins.

12. The method according to claim 11, further comprising forming a dielectric layer on the substrate to a height below the active height of the plurality of fins.

13. The method according to claim 8, wherein a width of each of the plurality of fins is the same or substantially the same.