Voltage droop mitigation in 3D chip system

• US 10,361,175 B2
• Filed: 02/09/2017
• Issued: 07/23/2019
• Est. Priority Date: 12/09/2013
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Xu, Yi, Hu, Xing, Xie, Yuan
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US15/428,536
• Publication Number:
  US 20170153916A1
• Time in Patent Office: 894 Days
• Field of Search: 716106, 716108-111, 716113, 716132-134, 716136
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

Claims

1. A method carried out by a 3D stacked chip system, for scheduling threads in the 3D stacked chip system, the method comprising the steps of:

(a) estimating intrinsic droop intensity of a plurality of threads from one or more applications;

(b) sorting the threads in descending order in terms of the intrinsic droop intensity and enqueuing them into a queue;

(c) selecting the thread at the head of the queue and placing it in an available core of the bottommost available die of the 3D stacked chip; and

(d) checking if the queue is empty, and repeating step (c) until the queue is empty.

2. The method of claim 1, wherein if multiple threads are estimated to have the same intrinsic droop intensity, employing a round-robin algorithm to choose threads from different applications to alleviate interference in horizontal direction.

3. The method of claim 1, further comprising departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.

4. The method of claim 2, further comprising departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.

5. A system for scheduling threads in a 3D stacked chip system, comprising:

means for estimating intrinsic droop intensity of a plurality of threads from one or more applications;

means for sorting the threads in descending order in terms of the intrinsic droop intensity and enqueuing them into a queue;

means for selecting the thread at the head of the queue and placing it in available core of the bottommost available die; and

means for checking if the queue is empty.

6. The system of claim 5, further comprising:

means for employing a round-robin algorithm to choose threads from different applications to alleviate interference in horizontal direction.

7. The system of claim 5, further comprising:

means for departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.

8. The system of claim 6, further comprising:

means for departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.