Semiconductor structure and device formed using selective epitaxial process

• US 10,361,201 B2
• Filed: 01/18/2016
• Issued: 07/23/2019
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Xie, Qi, Machkaoutsan, Vladimir, Maes, Jan Willem
• Primary Examiner(s): Wright, Tucker J
• Application Number:
  US14/997,683
• Publication Number:
  US 20160133628A1
• Time in Patent Office: 1,282 Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions

Abstract

Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both n-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.

Claims

1. A semiconductor structure comprising:

a substrate comprising silicon;

a strain relaxed buffer layer comprising Si<sub>1−

x</sub>Ge_x, where x is greater than 0 to about 0.5, overlying and in contact with the substrate;

a p well region formed within the buffer layer;

an n well region formed within the buffer layer;

one or more fin structures comprising a portion of the p well region and a layer consisting of silicon, the layer consisting of silicon being disposed directly over the p well region;

one or more fin structures comprising a portion of the n well region and a layer comprising Si<sub>1−

y</sub>Ge_y, the layer comprising Si<sub>1−

y</sub>Ge_y being disposed directly over the n well region, where y ranges from about 0.1 to 1; and

an insulating layer formed directly overlying a portion of the p well region and the n well region.

2. The semiconductor structure of claim 1, wherein the insulating layer is formed at a temperature of less than about 400°

C.

3. The semiconductor structure of claim 1, wherein the insulating layer is formed using H₂Si[N(C₂H₅)₂]₂ and an O₂ plasma.

4. The semiconductor structure of claim 1, wherein a thickness of the buffer layer within the one or more fin structures formed using the p well region and a layer consisting of silicon and the one or more fin structures formed using the n well region and a layer comprising Si₁₋

yGe_y is about 20 nm to about 200 nm.

5. The semiconductor structure of claim 1, wherein the buffer layer is formed using dichlorosilane (SiH₂Cl₂), germane (GeH₄), and hydrogen (H₂).

6. A CMOS device comprising:

a substrate comprising silicon;

a strain relaxed buffer layer comprising Si<sub>1−

x</sub>Ge_x, where x is greater than 0 to about 0.5, overlying and in contact with the substrate;

a p well region formed within the buffer layer;

an n well region formed within the buffer layer;

one or more fin structures comprising a portion of the p well region and a layer consisting of silicon, the layer consisting of silicon being disposed directly over the p well region;

one or more fin structures comprising a portion of the n well region and a layer comprising Si<sub>1−

y</sub>Ge_y, the layer comprising Si<sub>1−

y</sub>Ge_y being disposed directly over the n well region, where y ranges from about 0.1 to 1; and

an insulating layer formed directly overlying a portion of the p well region and the n well region.

7. The CMOS device of claim 6, wherein the insulating layer comprises silicon oxide.

8. The CMOS device of claim 6, wherein the insulating layer is formed at a temperature of less than about 400°

C.

9. The CMOS device of claim 6, wherein the insulating layer is formed using H₂Si[N(C₂H₅)₂]₂ and an O₂ plasma.