Memory cells and memory arrays

• US 10,361,204 B2
• Filed: 06/12/2018
• Issued: 07/23/2019
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mathew, Suraj J., Singanamalla, Raghunath, Ahmed, Fawad, Brown, Kris K., Nair, Vinay, Yang, Gloria, Slmsek-Ege, Fatma Arzum, Tran, Diem Thy N.
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US16/006,301
• Publication Number:
  US 20180301454A1
• Time in Patent Office: 406 Days
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Claims

1. A memory cell comprising:

a three-transistor-one-capacitor (3T-1C) configuration;

the three transistors of the 3T-1C configuration being a first transistor, a second transistor and a third transistor;

the second and third transistors being vertically displaced relative to one another;

a semiconductor pillar extending along the second and third transistors and comprising channel regions and source/drain regions of the second and third transistors;

the capacitor of the 3T-1C configuration having an inner node, an outer node, and a dielectric material between the inner and outer nodes;

the outer node being electrically coupled with a source/drain region of the first transistor and with a gate of the second transistor; and

wherein the first transistor is between the capacitor and a bitline, wherein the inner node of the capacitor is electrically coupled with an electrically conductive structure at a common plate voltage, and wherein the semiconductor pillar has an end against said electrically conductive structure.

2. A memory array, comprising:

an electrically conductive rail at a common plate voltage, with the rail extending along a mirror plane;

a bitline vertically spaced from the conductive rail;

a first memory cell which includes;

a capacitor under the electrically conductive rail;

the capacitor having an inner node, an outer node, and a capacitor dielectric material between the inner and outer nodes;

the inner node being electrically coupled with the electrically conductive rail;

a first transistor under the capacitor and comprising a first channel region between first and second source/drain regions;

the first transistor being over the bitline;

the first source/drain region being electrically coupled with the bitline, and the second source/drain region being electrically coupled with the outer node;

a second transistor having a second transistor gate electrically coupled with the outer node;

the second transistor comprising a second channel region between third and fourth source/drain regions;

a third transistor under the second transistor;

the third transistor comprising a third channel region between fifth and sixth source/drain regions;

a semiconductor pillar extending along the second and third gates;

the second and third channel regions being within semiconductor material of the semiconductor pillar;

the third, fourth, fifth and sixth source/drain regions being within the semiconductor material of the semiconductor pillar; and

the semiconductor pillar being against the bitline, the sixth source/drain region being electrically coupled with the bitline; and

a second memory cell on an opposing side of the electrically conductive rail from the first memory cell, with the second memory cell being substantially a mirror image of the first memory cell across the mirror plane;

the second memory cell sharing the electrically conductive rail with the first memory cell.

3. The memory cell of claim 2 wherein a gate of the third transistor is configured to have at least one bent region, and one or more extension regions that extend along the third channel region from said at least one bent region;

and wherein the gate of the third transistor and the one or more extension regions together form a substantially T-shaped configuration, substantially shelf-shaped configuration or substantially U-shaped configuration.