Fabrication of a strained region on a substrate

• US 10,361,304 B2
• Filed: 06/18/2018
• Issued: 07/23/2019
• Est. Priority Date: 08/02/2016
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lauer, Isaac, Liu, Jiaxing, Mo, Renee T.
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Fox, Brandon C
• Application Number:
  US16/011,124
• Publication Number:
  US 20180308976A1
• Time in Patent Office: 400 Days
• Field of Search: 257347, 438455
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02428 Structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

Claims

1. A method of forming a strained channel for a field effect transistor, comprising:

removing a sacrificial slab from a stack of a channel block on the sacrificial slab, and a stressor island on the channel block, wherein the sacrificial slab is between the channel block and a substrate, wherein the sacrificial slab has a single crystal structure, and wherein the channel block physically bonds to the substrate surface; and

heat treating the channel block and substrate to chemically bond the channel block to the substrate surface.

2. The method of claim 1, wherein the substrate has a single crystal structure.

3. The method of claim 1, wherein the stressor island is silicon nitride (SiN), and a stress is applied to the channel block by the stressor island.

4. The method of claim 1, wherein the sacrificial slab is silicon-germanium (SiGe).

5. The method of claim 1, wherein the channel block is single crystal silicon formed on the sacrificial slab by a heteroepitaxial growth process.

6. The method of claim 1, wherein a selective etch using gaseous hydrogen chloride (HCl) removes the sacrificial slab to release the channel block and stressor island from the substrate.

7. The method of claim 1, wherein the channel block has a thickness in a range of about 5 nm to about 100 nm, and the stressor island has a thickness equal to or greater than the channel block.

8. The method of claim 1, wherein the sacrificial slab has a thickness in the range of about 10 nm to about 100 nm.

9. The method of claim 1, wherein the heat treating is conducted at a temperature in a range of about 300 °

C. to about 750 °

C. for a duration in a range of about 1 hour to about 18 hours.

10. The method of claim 9, wherein the heat treating is an anneal at about 400 °

C. for about 6 hours.

11. A method of forming a strained channel, comprising:

forming a silicon-germanium sacrificial slab on a substrate surface, a channel block on the sacrificial slab, and a stressor island on the channel block; and

removing the silicon-germanium sacrificial slab using a selective etch to release the channel block and stressor island from the substrate, wherein the released channel block physically bonds to the substrate surface.

12. The method of claim 11, wherein the channel block has a thickness in the range of about 5 nm to about 100 nm, and the stressor island has a thickness in the range of about 5 nm to about 100 nm, where the stressor island is at least as thick as the channel block.

13. The method of claim 11, wherein the stressor island is silicon nitride (SiN), and a stress is applied to the channel block by the stressor island.

14. The method of claim 11, wherein the substrate is single crystal silicon and the surface is a <

100>

surface.

15. The method of claim 11, wherein the selective etch uses a solution made of a hydrofluoric acid (HF) solution, a hydrogen peroxide (H₂O₂) solution, and acetic acid (CH₃COOH).

16. An intermediate channel structure, comprising;

a substrate with a single crystal surface;

one or more pillars, where each of the one or more pillars supports a channel block; and

a stressor island on each channel block, wherein the stressor island applies a tensile or compressive stress to a top surface of the channel block to induce a strain in the channel block of about 0.5% to about 2%, wherein the stressor island is silicon nitride (SiN).

17. The intermediate device structure of claim 16, wherein each channel block has a thickness in the range of about 5 nm to about 100 nm, and the stressor island is at least as thick as the channel block.

18. The intermediate device structure of claim 16, wherein the stressor island applies a tensile stress to a top surface of the channel block in the range of about +1.6 GPa to about —

3 GPa.

19. The intermediate device structure of claim 16, wherein the substrate is a single crystal silicon wafer, the channel blocks are silicon channel blocks, and the one or more pillars are silicon-germanium pillars.