Transceiver for communication and method for controlling communication

• US 10,361,793 B2
• Filed: 07/25/2018
• Issued: 07/23/2019
• Est. Priority Date: 03/14/2016
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Tomita, Kazuhiro, Inui, Masuo
• Primary Examiner(s): Aghdam, Freshteh N
• Application Number:
  US16/045,460
• Publication Number:
  US 20190097738A1
• Time in Patent Office: 363 Days
• CPC Class Codes: H04B 1/3822 specially adapted for use in vehicles H04B1/3827 takes precedence
• CPC Class Codes: H04B 15/005 Reducing noise, e.g. humm, from the supply
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4906 using binary codes
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Claims

1. A clock extension peripheral interface (CXPI) communication circuit comprising:

a clock rise detector configured to detect a change of a signal on a CXPI communication bus from a low level to a high level, the signal generated by modulation of a timing signal from a master circuit;

a timing module configured to determine a second time for which the signal is at a low level and to compare the second time to a first time;

an encoder configured to extend a length of time the signal is at the low level by changing a data signal to be output to the CXPI communication bus from the high level to the low level, the data signal for pulling the signal on the CXPI communication bus to the low level; and

a timing adjustment module configured to change the data signal to the low level at the second time.

2. The CXPI communication circuit of claim 1, wherein the timing module computes a predetermined difference value of the second time from the first time based on a frequency at which a harmonic level is reduced and a natural number.

3. The CXPI communication circuit of claim 1, further comprising:

a timing signal start detection module configured to detect a rising edge of the signal; and

a timing signal start determination module configured to determine the first time based on a signal interval of the signal detected by the timing signal start detection module.

4. The CXPI communication circuit of claim 3, wherein the timing signal start detection module comprises:

a first comparator configured to compare a voltage level of the signal with a first reference voltage;

a second comparator configured to compare the voltage level with a second reference voltage, the second reference voltage different from the first reference voltage; and

the timing signal start determination module configured to determine a start of a change of the signal from the low level based on a comparison of the first comparator and the second comparator.

5. The CXPI communication circuit of claim 1, wherein the timing module determines the second time after a rising edge of the signal.

6. The CXPI communication circuit of claim 5, further comprising:

a first comparator configured to compare a voltage level of the signal with a first reference voltage;

a second comparator configured to compare the voltage level with a second reference voltage different from the first reference voltage; and

a timing signal start determination module configured to detect a change of the signal from the low level to the high level based on a comparison result from the first comparator and the second comparator.

7. The CXPI communication circuit of claim 1, wherein the timing module determines the second time to be earlier than a rising edge of the signal.

8. The CXPI communication circuit of claim 1, wherein the timing module determines a time of a rising edge of the signal to be a predetermined length of time after a timing of the change of the signal from the high level to the low level.

9. The CXPI communication circuit of claim 1, wherein a transceiver for CXPI bus communication is coupled to a bus with at least one other CXPI communication circuit.

10. The CXPI communication circuit of claim 9, wherein the transceiver functions as a slave node transceiver communicating with a master node transceiver over the communication bus.

11. A method for controlling communication by a transceiver over a clock extension peripheral interface (CXPI) communication bus, the method comprising:

detecting a falling edge of a bus signal generated by modulation of a timing signal and an input from the CXPI communication bus;

determining a second duration having a predetermined time difference from a first duration, the second and first durations indicative of a time between the falling edge and a rising edge on the bus signal occurring;

extending a second level of the bus signal by changing the data signal to be output to the CXPI communication bus from a first level to the second level.

12. The method of claim 11, wherein the predetermined time difference is computed based on a frequency at which a harmonic level is reduced and a natural number.

13. The method of claim 11, further comprising:

detecting a rising edge of the bus signal by a detector module; and

determining the first time based on a time of the rising edge.

14. The method of claim 11, wherein:

the transceiver includes a first comparator and a second comparator; and

the method further comprises;

comparing with the first comparator a voltage level of the bus signal with a first reference voltage,

comparing the voltage level with a second reference voltage with the second comparator, the second reference voltage substantially different from the first reference voltage, and

determining a time of a rising edge of the bus signal based on a comparison result from the first comparator and the second comparator.

15. The method of claim 11, further comprising determining the second time to be after the falling edge of the bus signal.

16. The method of claim 15, wherein:

the transceiver includes a first comparator and a second comparator; and

the method further comprises;

comparing with the first comparator a voltage level of the bus signal with a first reference voltage,

comparing with the second comparator the voltage level of the bus signal with a second reference voltage, the second reference voltage substantially different from the first reference voltage, and

determining a time of falling edge of the bus signal based on a comparison result from the first comparator and the second comparator.

17. The method of claim 11, further comprising determining the second time to be earlier than a time of a rising edge of the bus signal.

18. The method of claim 11, further comprising determining a time of a rising edge of the bus signal to be a predetermined length of time after the falling edge of the bus signal.

19. The method of claim 11, wherein the transceiver is coupled to a bus with at least one other transceiver.

20. The method of claim 19, wherein the transceiver functions as a slave node transceiver communicating with a master node transceiver over the CXPI communication bus.