Transceiver for communication and method for controlling communication
First Claim
1. A clock extension peripheral interface (CXPI) communication circuit comprising:
- a clock rise detector configured to detect a change of a signal on a CXPI communication bus from a low level to a high level, the signal generated by modulation of a timing signal from a master circuit;
a timing module configured to determine a second time for which the signal is at a low level and to compare the second time to a first time;
an encoder configured to extend a length of time the signal is at the low level by changing a data signal to be output to the CXPI communication bus from the high level to the low level, the data signal for pulling the signal on the CXPI communication bus to the low level; and
a timing adjustment module configured to change the data signal to the low level at the second time.
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Accused Products
Abstract
An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.
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Citations
20 Claims
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1. A clock extension peripheral interface (CXPI) communication circuit comprising:
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a clock rise detector configured to detect a change of a signal on a CXPI communication bus from a low level to a high level, the signal generated by modulation of a timing signal from a master circuit; a timing module configured to determine a second time for which the signal is at a low level and to compare the second time to a first time; an encoder configured to extend a length of time the signal is at the low level by changing a data signal to be output to the CXPI communication bus from the high level to the low level, the data signal for pulling the signal on the CXPI communication bus to the low level; and a timing adjustment module configured to change the data signal to the low level at the second time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for controlling communication by a transceiver over a clock extension peripheral interface (CXPI) communication bus, the method comprising:
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detecting a falling edge of a bus signal generated by modulation of a timing signal and an input from the CXPI communication bus; determining a second duration having a predetermined time difference from a first duration, the second and first durations indicative of a time between the falling edge and a rising edge on the bus signal occurring; extending a second level of the bus signal by changing the data signal to be output to the CXPI communication bus from a first level to the second level. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification