Transmission and reception methods for a binary signal on a serial link

• US 10,361,890 B2
• Filed: 10/11/2018
• Issued: 07/23/2019
• Est. Priority Date: 12/04/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Arnal, Christophe, Van Der Tuijn, Roland
• Primary Examiner(s): Perez, James M
• Application Number:
  US16/157,428
• Publication Number:
  US 20190044758A1
• Time in Patent Office: 285 Days
• Field of Search: 375238, 375354-376
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: H04B 10/0795 Performance monitoring; Measurement of transmission parameters
• CPC Class Codes: H04L 25/0262 Arrangements for detecting the data rate of an incoming signal

Abstract

A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.

Claims

1. A method comprising:

causing a first transition of a serial link from a first state to a second state, the first transition being cause by a transmitter capable of transmitting at a plurality of different speeds of transmission;

a first time after the first transition, using the transmitter to cause a second transition of the serial link to the first state; and

a second time after the second transition, using the transmitter to transmit a plurality of bits through the serial link, wherein the first time indicates a selected speed of transmission, and wherein a bit of the plurality of bits has a first duration based on the first time.

2. The method of claim 1, wherein the first time plus the second time is substantially equal to a start bit time, and wherein the first time is between 60% and 90% of the start bit time.

3. The method of claim 1, wherein the first time plus the second time is substantially equal to the first duration times k, wherein k is a positive integer.

4. The method of claim 3, wherein k is equal to 4.

5. The method of claim 1, wherein each of the plurality of bits has the same duration.

6. The method of claim 1, wherein the first duration is substantially equal to the first time over α

, and wherein α

is a predetermined factor, the method further comprising;

detecting a third transition of the serial link from the first state to the second state using a receiver;

measuring a third time between the third transition and a fourth transition of the serial link from the second state to the first state; and

a fourth time after the fourth transition, receiving the plurality of bits.

7. The method of claim 6, further comprising determining a duration of a start bit as the third time over α

.

8. The method of claim 7, further comprising dividing the start bit over k to determine a duration of a bit of the received plurality of bits, wherein k is a positive integer.

9. A transmitter capable of transmitting at a plurality of different speeds of transmission and configured to be coupled to a serial link, the transmitter comprising at least one processing unit configured to:

cause a first transition in the serial link from a first state to a second state;

a first time after the first transition, cause a second transition in the serial link to the first state; and

a second time after the second transition, transmit a plurality of bits through the serial link, wherein the first time indicates a selected speed of transmission, and wherein a bit of the plurality of bits has a first duration based on the first time.

10. The transmitter of claim 9, wherein the first time plus the second time is substantially equal to a start bit time, and wherein the first time is between 60% and 90% of the start bit time.

11. The transmitter of claim 9, wherein the first time plus the second time is substantially equal to the first duration times k, wherein k is a positive integer.

12. The transmitter of claim 11, wherein k is equal to 4.

13. The transmitter of claim 9, wherein the first duration is substantially equal to the first time over α

, and wherein α

is a predetermined factor, the transmitter further configured to cause a third transition in the serial link to the first state during transmission of a first bit of the plurality of bits, wherein the third transition occurs (1+α

) times the first duration after the first transition.

14. The transmitter of claim 13, further configured to cause a fourth transition in the serial link to the second state during transmission of a third bit of the plurality of bits, wherein the fourth transition occurs (3+α

) times the first duration after the first transition.

15. The transmitter of claim 9, further configured to cause an additional transition in the serial link during each bit of the plurality of bits.

16. A receiver configured to be coupled to a serial link, the receiver comprising at least one processing unit configured to:

detect a first transition of the serial link from a first state to a second state;

determine a first time between the first transition and a second transition of the serial link from the second state to the first state;

divide the first time over α

to estimate a duration of a start bit, wherein α

is a predetermined factor;

determine a second time based on the first time and α

; and

receive a plurality of bits after the second time.

17. The receiver of claim 16, wherein the receiver is further configured to determine a duration of a bit of the plurality of bits by dividing the duration of the start bit over k, wherein k is a positive integer.

18. The receiver of claim 17, wherein k is equal to 4.

19. The receiver of claim 16, wherein α

is between 0.6 and 0.9.

20. The receiver of claim 16, wherein the plurality of bits have the same duration.

21. The receiver of claim 16, further configured to:

determine a third time between the first transition and a third transition of the serial link to the first state, wherein the third transition occurs during reception of a first bit of the plurality of bits;

generate a second estimate of the duration of the start bit by dividing the third time over (1+α

);

determine a fourth time based on the third time; and

after the fourth time, receive a second bit of the plurality of bits.

22. The receiver of claim 21, further configured to:

determine a fifth time between the first transition and a fourth transition of the serial link to the second state, wherein the fourth transition occurs during reception of a third bit of the plurality of bits;

generate a third estimate of the duration of the start bit by dividing the fifth time over (3+α

);

determine a sixth time based on the fifth time; and

after the sixth time, receive a fourth bit of the plurality of bits.

23. The receiver of claim 16, further configured to:

determine, for each bit, a respective first bit time portion extending between a start of a respective bit and an additional transition occurring during the respective bit; and

determine a respective second bit time portion extending from the additional transition based on the first bit time portion and α

.