Focal plane array processing method and apparatus

• US 10,362,254 B2
• Filed: 10/07/2016
• Issued: 07/23/2019
• Est. Priority Date: 10/27/2006
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Kelly, Michael, Tyrrell, Brian, Colonero, Curtis, Berger, Robert, Schultz, Kenneth, Wey, James, Mooney, Daniel, Candell, Lawrence
• Primary Examiner(s): Pyo, Kevin K
• Application Number:
  US15/288,492
• Publication Number:
  US 20170026603A1
• Time in Patent Office: 1,019 Days
• Field of Search: 2502081, 257292, 348294, 348297, 348302, 348308
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11B 20/00086 Circuits for prevention of unauthorised reproduction or copying, e.g. piracy indicating unauthorised use of record carriers in general G11B23/28; scrambling for television signal recording H04N5/913; network architectures or network protocols for network security H04L63/00; cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
• CPC Class Codes: G11B 20/0021 involving encryption or decryption of contents recorded on or reproduced from a record carrier
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
• CPC Class Codes: H04L 9/12 Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/4223 Cameras H04N23/00 takes precedence
• CPC Class Codes: H04N 21/4408 involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
• CPC Class Codes: H04N 23/20 for generating image signals from infrared radiation only
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/707 Pixels for event detection
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure
• CPC Class Codes: H04N 5/913 : for scrambling ; for copy protection

Abstract

A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.

Claims

1. An apparatus comprising:

a two-dimensional array of photodetectors; and

a two-dimensional array of analog-to-digital converters (ADCs) operably coupled to the two-dimensional array of photodetectors,

wherein at least one ADC in the two-dimensional array of ADCs comprises;

a modulo M counter to store a count value representing a current generated by a corresponding photodetector in the two-dimensional array of photodetectors, and

wherein the apparatus is configured to perform image differencing based on the count value stored in the modulo M counter.

2. The apparatus of claim 1, wherein M is the product of two prime numbers.

3. The apparatus of claim 1, wherein the modulo M counter is a bidirectional counter.

4. The apparatus of claim 1, wherein the at least one ADC further comprises a capacitor to integrate the current generated by the corresponding photodetector.

5. The apparatus of claim 4, wherein the at least one ADC further comprises at least one of a voltage-to-frequency converter or a comparator to convert a voltage across the capacitor to a signal that increments or decrements the count value stored in the modulo M counter.

16. The apparatus of claim 1, wherein the count value is an integer remainder of a division by M.

17. The apparatus of claim 1, wherein the modulo M counter is configured to change the count value stored in the modulo M counter to 0 in response to the count value surpassing M.

18. The apparatus of claim 1, wherein the modulo M counter comprises a linear feedback shift register.

19. The apparatus of claim 1, wherein the modulo M counter defines a virtual well depth W_virt representing an amount of charge that can be accumulated and digitized before a readout.

20. The apparatus of claim 19, wherein the virtual well depth W_virt is given by:

6. A method comprising:

generating a photocurrent with a photodetector in a two-dimensional array of photodetectors;

converting the photocurrent into a digital signal with an analog-to-digital converter (ADC) in a two-dimensional array of ADCs;

storing a count value representing the digital signal in a modulo M counter operably coupled to the ADC; and

performing image differencing based at least in part on the count value stored in the modulo M counter.

7. The method of claim 6, wherein storing the count value comprises storing an integer remainder of a division by M.

8. The method of claim 6, wherein M is the product of two prime numbers.

9. The method of claim 6, wherein storing the count value comprises at least one of incrementing or decrementing the modulo M counter in response to the digital signal.

10. The method of claim 6, wherein converting the photocurrent comprises integrating the photocurrent with a capacitor.

11. The method of claim 10, wherein converting the photocurrent further comprises converting a voltage across the capacitor to yield the digital signal.

12. The method of claim 6, further comprising:

changing the count value stored in the modulo M counter to 0 in response to the digital count value surpassing M.

13. The method of claim 6, further comprising reading the modulo M counter before accumulating an amount of charge equal to a virtual well depth W_virt:

14. The method of claim 6, further comprising:

determining, based on the image differencing, a velocity of an object in a scene imaged by the two-dimensional array of photodetectors.

15. The method of claim 6, further comprising:

determining, based on the image differencing, a difference between a scene imaged by the two-dimensional array of photodetectors and a reference image.