Architectures for an implantable stimulator device having a plurality of electrode driver integrated circuits with shorted electrode outputs

• US 10,363,422 B2
• Filed: 04/19/2017
• Issued: 07/30/2019
• Est. Priority Date: 01/16/2012
• Status: Active Grant

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: Feldman, Emanuel, Parramon, Jordi, Griffith, Paul J., Shi, Jess, Tong, Robert, Marnfeldt, Goran
• Primary Examiner(s): Kahelin, Michael W
• Application Number:
  US15/491,492
• Publication Number:
  US 20170216600A1
• Time in Patent Office: 832 Days
• CPC Class Codes: A61N 1/05 for implantation or insertion into the body, e.g. heart electrode A61N1/06 takes precedence
• CPC Class Codes: A61N 1/0534 Electrodes for deep brain stimulation
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/36171 Frequency
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Claims

1. An implantable stimulator device, comprising:

a plurality of electrode nodes;

a first timing channel dedicated to operate with first stimulation circuitry, wherein the first timing channel is configured to program the first stimulation circuitry to provide first current pulses, and to select a first plurality of the plurality of electrode nodes to receive the first current pulses; and

a second timing channel dedicated to operate with second stimulation circuitry, wherein the second timing channel is configured to program the second stimulation circuitry to provide second current pulses, and to select a second plurality of the plurality of electrode nodes to receive the second current pulses,

wherein if an electrode node is common to both the selected first plurality of electrode nodes and the second plurality of electrode nodes, the first and second current pulses are added at the common electrode node when they overlap.

2. The device of claim 1, wherein the first current pulses are of a first frequency, and wherein the second current pulses are of a second frequency.

3. The device of claim 1, wherein the first timing channel and the first stimulation circuitry comprises a first integrated circuit, and wherein the second timing channel and the second stimulation circuitry comprises a second integrated circuit.

4. The device of claim 3, wherein the first and second integrated circuits are housed in a single package.

5. The device of claim 1, wherein the first stimulation circuitry is programmed by the first timing channel with timing information of the second current pulses, and wherein the second stimulation circuitry is programmed by the second timing channel with timing information of the first current pulses.

6. The device of claim 1, wherein the first stimulation circuitry further comprises first recovery circuitry for recovering charge after provision of the first current pulses, and wherein the second stimulation circuitry further comprises second recovery circuitry for recovering charge after provision of the second current pulses.

7. The device of claim 6, wherein the first recovery circuitry is configured to be inactivated during the second current pulses, and wherein the second recovery circuitry is configured to be inactivated during the first current pulses.

8. The device of claim 1, wherein the electrode nodes are coupled to electrodes for delivering the current provided by each stimulation circuitry to the tissue of a patient.

9. The device of claim 8, wherein the electrode nodes are coupled to the electrodes via decoupling capacitors.

10. The device of claim 1, further comprising:

a case for housing the electrode nodes and the first and second stimulation circuitries; and

at least one array comprising electrodes for stimulating a patient'"'"'s tissue,

wherein one electrode node is coupled to the case, and wherein the other of the plurality of electrode nodes are coupled to electrodes on the at least one electrode array.

11. The device of claim 1, further comprising a conductive case for housing the first and second stimulation circuitries, wherein the conductive case comprises one of the plurality of electrode nodes, wherein conductive case is common to both the selected first plurality of electrode nodes and the second plurality of electrode nodes.

12. An implantable stimulator device, comprising:

a plurality of electrode nodes;

first stimulation circuitry programmed to provide first current pulses, and to select a first plurality of the plurality of electrode nodes to receive the first current pulses; and

second stimulation circuitry programmed to provide second current pulses, and to select a second plurality of the plurality of electrode nodes to receive the second current pulses,

wherein if an electrode node is common to both the selected first plurality of electrode nodes and the second plurality of electrode nodes, the first and second current pulses are added at the common electrode node when they overlap, and

wherein the first stimulation circuitry is programmed with timing information of the second current pulses, and wherein the second stimulation circuitry is programmed with timing information of the first current pulses.

13. The device of claim 12, wherein the first current pulses are of a first frequency, and wherein the second current pulses are of a second frequency.

14. The device of claim 12, wherein the first stimulation circuitry comprises a first integrated circuit, and wherein the second stimulation circuitry comprises a second integrated circuit.

15. The device of claim 12, further comprising:

a case for housing the electrode nodes and the first and second stimulation circuitries; and

at least one array comprising electrodes for stimulating a patient'"'"'s tissue,

wherein one electrode node is coupled to the case, and wherein the other of the plurality of electrode nodes are coupled to electrodes on the at least one electrode array.

16. The device of claim 12, further comprising a conductive case for housing the first and second stimulation circuitries, wherein the conductive case comprises one of the plurality of electrode nodes, wherein conductive case is common to both the selected first plurality of electrode nodes and the second plurality of electrode nodes.

17. An implantable stimulator device, comprising:

a plurality of electrode nodes;

first stimulation circuitry programmed to provide first current pulses, and to select a first plurality of the plurality of electrode nodes to receive the first current pulses; and

second stimulation circuitry programmed to provide second current pulses, and to select a second plurality of the plurality of electrode nodes to receive the second current pulses,

wherein if an electrode node is common to both the selected first plurality of electrode nodes and the second plurality of electrode nodes, the first and second current pulses are added at the common electrode node when they overlap,

wherein the first stimulation circuitry further comprises first recovery circuitry for recovering charge after provision of the first current pulses, and wherein the second stimulation circuitry further comprises second recovery circuitry for recovering charge after provision of the second current pulses, and

wherein the first recovery circuitry is configured to be inactivated during the second current pulses, and wherein the second recovery circuitry is configured to be inactivated during the first current pulses.

18. The device of claim 17, wherein the first current pulses are of a first frequency, and wherein the second current pulses are of a second frequency.

19. The device of claim 17, wherein the first stimulation circuitry comprises a first integrated circuit, and wherein the second stimulation circuitry comprises a second integrated circuit.

20. The device of claim 17, further comprising a conductive case for housing the first and second stimulation circuitries, wherein the conductive case comprises one of the plurality of electrode nodes, wherein conductive case is common to both the selected first plurality of electrode nodes and the second plurality of electrode nodes.