Array substrate, display panel and display device

• US 10,365,743 B2
• Filed: 10/19/2017
• Issued: 07/30/2019
• Est. Priority Date: 06/29/2017
• Status: Active Grant

• Current Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: Pan, Chaohuang, Cao, Zhaokeng, Zhou, Zhiwei
• Primary Examiner(s): Patel, Sanjiv D.
• Application Number:
  US15/787,970
• Publication Number:
  US 20180039364A1
• Time in Patent Office: 649 Days
• CPC Class Codes: G02F 1/133388 with constructional differences between the display region and the peripheral region
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13456 Cell terminals located on one side of the display only
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: H01L 2224/06155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

An array substrate, a display panel and a display device are provided. The array substrate includes a display area and a non-display area surrounding the display area. The display area includes a plurality of data lines and a plurality of first touch electrodes. A plurality of data signal lines and a plurality of discrete pads are provided in a first non-display area at a side of the display area. Each data signal line is connected to at least one data line, each pad is electrically connected to a respective data signal line, and at least one pad is electrically connected to a respective first touch electrode. The pads are configured to supply a data signal to the data lines in a display phase and to supply a touch signal to the first touch electrodes in a touch phase.

Claims

1. An array substrate, comprising a display area and a non-display area surrounding the display area,

wherein the non-display area comprises a first non-display area and a second non-display area opposite to the first non-display area;

wherein the display area comprises a plurality of data lines, a plurality of touch lines, and a plurality of first touch electrodes;

wherein a plurality of data signal lines and a plurality of discrete pads are provided in the first non-display area;

wherein each of the plurality of data signal lines is connected to at least one of the plurality of data lines, the plurality of discrete pads each is electrically connected to one of the plurality of data signal lines respectively, and at least one of the plurality of discrete pads is electrically connected to one of the plurality of first touch electrodes; and

wherein the plurality of discrete pads are configured to supply a data signal to the plurality of data lines in a display phase and to supply a touch signal to the plurality of first touch electrodes in a touch phase;

wherein the array substrate further comprises;

a plurality of first thin film transistor groups in the first non-display area and a plurality of second thin film transistor groups disposed in the second non-display area;

wherein each of the plurality of second thin film transistor groups comprises at least one second thin film transistor, a first electrode of the at least one second thin film transistor is connected to one of the plurality of data lines, and wherein a second electrode of each of the at least one second thin film transistor is connected to a same first touch electrode via one of the plurality of touch lines;

wherein each of the plurality of discrete pads connects to at least one of the plurality of data lines, wherein the at least one second thin film transistor connected to the at least one data line is in a same second thin film transistor group.

2. The array substrate of claim 1, wherein a plurality of touch signal lines are provided at least in the first non-display area, and wherein the plurality of touch lines connected to a same touch signal line are connected to a same first touch electrode;

and

wherein the plurality of first thin film transistor groups each comprises at least one first thin film transistor, a first electrode of the at least one first thin film transistor is connected to one of the plurality of pads, and a second electrode of the at least one first thin film transistor is connected to a same touch signal line.

3. The array substrate of claim 2, wherein gate electrodes of the at least one first thin film transistor in the plurality of first thin film transistor groups are connected to a same control signal line.

4. The array substrate of claim 1, wherein gate electrodes of the at least one second thin film transistors in the plurality of second thin film transistor groups are connected to a same control signal line.

5. The array substrate of claim 1, wherein at least two of the plurality of pads are electrically connected to a same first touch electrode.

6. The array substrate of claim 1, further comprising a plurality of third thin film transistor groups disposed in the first non-display area, wherein the plurality of third thin film transistor groups each includes at least one third thin film transistor, and wherein the at least one third thin film transistor in the plurality of third thin film transistor groups is associated with one second thin film transistor in the plurality of second thin film transistor groups;

and

wherein a first electrode of the at least one third thin film transistor is electrically connected to the second electrode of an associated second thin film transistor via one of the plurality of touch lines, and a second electrode of the at least one third thin film transistor is electrically connected to one of the plurality of first data lines that is connected to a first electrode of the associated second thin film transistor.

7. The array substrate of claim 6, wherein gate electrodes of all the at least one third thin film transistors in the plurality of third thin film transistor groups are connected to a same control signal line.

8. The array substrate of claim 1 wherein a plurality of fourth thin film transistor groups are provided in the first non-display area, wherein each of the plurality of fourth thin film transistor groups comprises at least two fourth thin film transistors, a first electrode of the at least two fourth thin film transistors each in one of the plurality of fourth thin film transistor groups is connected to one of plurality of pads, and second electrodes of the at least two fourth thin film transistors in each of the plurality of fourth thin film transistor groups are connected to each other.

9. The array substrate of claim 8, wherein gate electrodes of all fourth thin film transistors in the plurality of fourth thin film transistor groups are connected to a same control signal line.

10. The array substrate of claim 1, wherein the plurality of second touch lines each overlays one of the plurality of first touch electrodes in a perpendicular direction of the array substrate.

11. The array substrate of claim 10, wherein each of the plurality of the touch lines is in electrical contact with an overlapping part between each of the plurality of the touch lines and the corresponding first touch electrode.

12. The array substrate of claim 10, wherein each of the plurality of the touch lines is electrically connected to the overlapping part between each of the plurality of the touch lines and the corresponding first touch electrode via a through-hole.

13. The array substrate of claim 1, further comprising a glass substrate, wherein the plurality of discrete pads are disposed on the glass substrate.

14. The array substrate of claim 1, wherein the plurality of first touch electrodes are touch driving electrodes or touch sensing electrodes arranged in parallel strips and extending in a direction same as the plurality of data lines.

15. The array substrate of claim 1, further comprising a common electrode shared as at least one of the plurality of first touch electrodes.

16. A display panel, comprising an array substrate, a color filter substrate opposite to the array substrate, and a control chip,

wherein the array substrate comprises a display area and a non-display area surrounding the display area;

wherein the display area comprises a plurality of data lines and a plurality of first touch electrodes;

wherein a plurality of data signal lines and a plurality of discrete pads are provided in a first non-display area at a side of the display area;

wherein each of the plurality of data signal lines is connected to at least one of the plurality of data lines, the plurality of discrete pads each is electrically connected to one of the plurality of data signal lines respectively, and at least one of the plurality of discrete pads is electrically connected to one of the plurality of first touch electrodes; and

wherein the plurality of discrete pads are configured to supply a data signal to the plurality of data lines in a display phase and to supply a touch signal to the plurality of first touch electrodes in a touch phase,

wherein the control chip is disposed in the first non-display area and covers a plurality of first thin film transistor groups or a plurality of fourth thin film transistor groups perpendicular to the array substrate; and

wherein each of a plurality of data output pins of the control chip is connected to one of the plurality of discrete pads respectively.

17. The display panel of claim 16, wherein second touch electrodes are provided at a side of the color filter substrate towards the array substrate, or at a side of the color filter substrate facing away from the array substrate;

wherein the plurality of first touch electrodes coordinate with the second touch electrodes in a touch detection.

18. A display device, comprising a display panel, wherein the display panel comprises an array substrate and a color filter substrate opposite to the array substrate,

wherein the array substrate comprises a display area and a non-display area surrounding the display area;

wherein the non-display area comprises a first non-display area and a second non-display area opposite to the first non-display area;

wherein the display area comprises a plurality of data lines, a plurality of touch lines, and a plurality of first touch electrodes;

wherein a plurality of data signal lines and a plurality of discrete pads are provided in the first non-display area;

wherein each of the plurality of data signal lines is connected to at least one of the plurality of data lines, the plurality of discrete pads each is electrically connected to one of the plurality of data signal lines respectively, and at least one of the plurality of discrete pads is electrically connected to one of the plurality of first touch electrodes; and

wherein the plurality of discrete pads are configured to supply a data signal to the plurality of data lines in a display phase and to supply a touch signal to the plurality of first touch electrodes in a touch phase;

wherein the array substrate further comprises;

a plurality of first thin film transistor groups in the first non-display area, a plurality of second thin film transistor groups disposed in the second non-display area, and a plurality of touch signal lines at least in the first non-display area;

wherein the plurality of touch lines connected to a same touch signal line are connected to a same first touch electrode;

wherein each of the plurality of second thin film transistor groups comprises at least one second thin film transistor, a first electrode of the at least one second thin film transistor is connected to one of the plurality of data lines and a second electrode of each of the at least one second thin film transistor is connected to a same first touch electrode via one of the plurality of touch lines;

wherein each of the plurality of discrete pads connects to at least one of the plurality of data lines, wherein the at least one second thin film transistor connected to the at least one data line is in a same second thin film transistor group.