Spin loop delay instruction

• US 10,365,929 B2
• Filed: 11/13/2017
• Issued: 07/30/2019
• Est. Priority Date: 03/08/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi Y., Jacobi, Christian, Saporito, Anthony, Schwarz, Eric M., Slegel, Timothy J.
• Primary Examiner(s): Pan, Daniel H
• Application Number:
  US15/810,826
• Publication Number:
  US 20180260228A1
• Time in Patent Office: 624 Days
• Field of Search: 712207-213
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/4806 Task transfer initiation or dispatching
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Claims

1. A computer-implemented method of facilitating processing within a computing environment, said computer-implemented method comprising:

decoding an instruction defined to be delayed, the instruction having a field associated therewith that indicates one or more conditions to be checked;

delaying dispatching of the instruction;

dispatching the instruction based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked;

determining that forward progress is to be made for a thread on which the instruction is to be dispatched; and

dispatching, based on determining that forward progress is to be made, the instruction prior to the timeout or waiting for the at least one condition to be met to force completion of the instruction.

2. The computer-implemented method of claim 1, wherein the one or more conditions comprise a time done condition, no broadcast operation in progress, no blocking translation, quiesce request received, quiesce has priority, quiesce fast mode request active, co-processor done, system operation done and error return code.

3. The computer-implemented method of claim 1, wherein the timeout comprises reaching a specified amount of delay, the specified amount of delay comprising a number of processing cycles.

4. The computer-implemented method of claim 3, wherein the number of processing cycles is provided in a register accessible by the instruction.

5. The computer-implemented method of claim 1, wherein the field is an immediate field of the instruction, the immediate field including at least one or more indicators for the at least one or more conditions, and wherein a set indicator indicates a condition corresponding thereto is to be checked.

6. The computer-implemented method of claim 1, further comprising checking the one or more conditions, based on dispatching the instruction prior to the timeout or meeting the at least one condition.

7. The computer-implemented method of claim 1, further comprising:

executing the instruction to completion, the executing comprising executing the instruction as a no-operation and indicating successful completion although the instruction did not delay as defined.

8. The computer-implemented method of claim 1, wherein the instruction comprises at least one operation code field to indicate a spin delay operation and an immediate field to indicate the one or more conditions to be checked.

9. The computer-implemented method of claim 1, further comprising checking the one or more conditions subsequent to completion of the instruction.